<h2>The customer programmed components</h2>
- <h3>The programmed controller</h3>
-
<p>The customer programmed portion of the programmed control consists of:</p>
<ol>
<li>default next state list</li>
<li>state dictionary</li>
<li>an initial state reference</li>
<li>a halt state reference</li>
+ <li>an error state reference</li>
</ol>
<p>A programmer uses a Natural Number to reference a state. Hence the initial state reference and halt state reference are set to Natural Numbers. It is not required but it is conventional to use 0 as the initial state.</p>
<li>write(<em>x</em>)</li>
</ol>
- <p>Note that the write value, <em>x</em must be a symbol from either the data alphabet or be the empty symbol.</p>
+ <p>Note that the write value, <em>x</em> must be a symbol from either the data alphabet or be the empty symbol.</p>
<p>The structural portion of the programmed controller:</p>
<ol>
<li>the reset control line</li>
<li>the clock</li>
<li>multiple comparators</li>
- <li>error state symbol</li>
</ul>
<p>The comparators are used to used to match the identifier with a the values read from each of the buffers. Note that if the same next state is specified for the same start state, then it is the same as though the identifiers are in disjunction. Also the no-op command to create conjunctive decisions. Hence as a shorthand notation arcs can be labeled with propositions made from the buffer values.</p>
- <p>Upon reset the <em>current state register</em> is written with the <em>initial state</em>. Upon each clock tick, the next state is written to the <em>current state register</em>. When the state controller reaches the halt state, the machine stops.</p>
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-
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- <p>
- Each state corresponds to a symbol. Here, instances of the state symbols appear in a different context than that of the data alphabet symbols or the empty symbol, and thus they do not need to be distinct from them. In real machines, state symbol instances are unsigned integers.
- </p>
-
- <p>
- The alphabet of states is specified in the architecture, and in the design stage becomes a table in a document where each row relates a bit vector with a name. It remains a documented abstraction to the designers, but can become embodied in programs where meaningful print statements are needed. Perhaps in a CAD tool such as a hardware debugger.
- </p>
+ <p>Upon reset the <em>current state register</em> is written with the <em>initial state</em>. When the <em>current state register</em> is set to the halt state, the machine stops. If no next state is found for a given state, the <em>error state</em> is written to the <em>current_state_register</em> and the machine halts.</p>
- <p>
- The current state register holds an instance of the current state symbol. During reset its value is forced to be an instance of the initial state symbol. During normal operation it is successively updated with the prior next state choice.
- </p>
+ <p>On the rising edge of the clock, the TTU writes the data and status buffers, and the state command is written to the TTU command buffer. On the falling edge of the clock, the TTU completes the state command, and the next state is written to the current state register.</p>
- <p>
- The current state register output is wired to the comparator, along with the halt symbol. A positive match across the comparator asserts a gating signal that halts the machine clock. This halts the internal procedures (discussed in a later chapter), which guarantees that no further step pulses will arrive at the programmed controller.
- </p>
-
- <p>
- The current state register is used to lookup a row in the instruction table. Each defined row contains an instruction that is sent to the tape transport unit. A retrieved instruction provides the specific control code and, in the case of a write instruction, the argument symbol to be written. If the current state yields no match in the instruction table, the logic defaults to issuing a 'no-op', no operation instruction. While a 'no-op' need not be physically acted upon by the tape transport, the fixed wiring typically propagates the signal regardless.
- </p>
-
- <p>
- The current state register, concatenated with the output of the read buffer, is used to lookup a row in the next state table. It yields the subsequent state, or an indication that the given input is not found.
- </p>
-
- <p>
- The current state register is also used to lookup a row in the default next state table while ignoring the read buffer output. An entry for a given state might not exist here either.
- </p>
-
- <p>
- The 'lookup' operation can be implemented in a number of ways, at the election of the design engineers. In the simplest form a lookup indexes into an array, though this can be inefficient. For such small machines a hash table is an unlikely alternative. More likely is content addressable memory, a programmable logic array, or custom combinational logic.
- </p>
-
- <p>
- The programmer must provide the state alphabet, the instruction table, and the next state table. To do this, the programmer benefits from understanding how the programmed controller works. When preparing to provide the tables, the programmer can draw a state machine graph. There are two styles of state machine graphs: the Mealy style and the Moore style. The Mealy style has outputs specified on the edges, while the Moore machine has outputs associated with states. They are equivalently expressive, though the Moore style more easily leads to the table values for the programmed controller described in this section.
- </p>
-
- <p>
- Each defined row of the instruction table specifies a state specific instruction to be given to the tape transport unit. The instruction will be one from the set: { no-op, step-left, step-right, and write(value) }, where the value parameter for a write instruction is coded directly as part of the instruction.
- </p>
+ <p>Here is an example customer defined programmed controller for incrementing a unary number:</p>
+ <RT·code>
+ Data alphabet: {s}
+ States: {0, 1, 2, 3, 4}
+ Initial state: 0
+ Halt state: 3
+ Error state: 4
+
+ State dictionary:
+ {
+ 0: n op
+ s -> 1
+ □ -> 2
+ 1: step_right
+ s -> 1
+ □ -> 2
+ 2: write(s)
+ * -> 3
+ }
+
+ Default next state table: {
+ status:left-of-leftmost -> 4
+ }
+ </RT·code>
<p>Upon entering a state, the value under the head is copied to the TTU side of the read buffer. The arc propositions are evaluated against this value.
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