From: Thomas Walker Lynch Date: Sat, 25 Jul 2026 09:00:35 +0000 (+0000) Subject: new patch panel diagrams X-Git-Url: https://git.reasoningtechnology.com/%5B%5E?a=commitdiff_plain;h=bf96fc1d1a527db651503684598317e96c043bf2;p=TM-2026 new patch panel diagrams --- diff --git a/document/book/TM-2026.html b/document/book/TM-2026.html index a920f6b..c97ab94 100644 --- a/document/book/TM-2026.html +++ b/document/book/TM-2026.html @@ -39,7 +39,7 @@

At a conference in Paris in 1900, David Hilbert presented a list of pressing unsolved problems in mathematics. - Second on his list was "The Compatibility of the Arithmetical Axioms." Hilbert challenged mathematicians to find a means to demonstrate that "a finite number of logical steps based upon them [axioms] can never lead to contradictory results" F. N. Cole et al., eds., Bulletin of the American Mathematical Society, Vol. 8 (New York: Macmillan, 1902). This can be found at https://www.gutenberg.org/cache/epub/71655/pg71655 images.html. The MathWorld article on this subject, https://mathworld.wolfram.com/HilbertsProblems.html, explains that Hilbert presented 10 problems at the conference, though the publication shows 23 problems, and shortly later a 24th problem was added. Based on the notes of this citation, it appears the second problem is the same on all of these lists. Also note, Hilbert discusses completeness specifically as an axiom for bounding on the sets, which appears to be distinct from the question of logical completeness for an axiomatic system.. + Second on his list was "The Compatibility of the Arithmetical Axioms." Hilbert challenged mathematicians to find a means to demonstrate that "a finite number of logical steps based upon them [axioms] can never lead to contradictory results" F. N. Cole et al., eds., Bulletin of the American Mathematical Society, Vol. 8 (New York: Macmillan, 1902). This can be found at https://www.gutenberg.org/cache/epub/71655/pg71655 images.html. The MathWorld article on this subject, https://mathworld.wolfram.com/HilbertsProblems.html, explains that Hilbert presented 10 problems at the conference, though the publication shows 23 problems, and shortly later a 24th problem was added. Based on the notes of this citation, it appears the second problem is the same on all of these lists. Also note, Hilbert discusses completeness specifically as an axiom for bounding on the sets, which appears to be distinct from the question of logical completeness for an axiomatic system..

@@ -119,7 +119,7 @@

- In reading Alan Turing's 1936 paper, it is striking how modern the text feels, specifically because he discusses algorithms, stored programs, and the mechanical limits of computation. + In reading Alan Turing's 1936 paper, it is striking how modern the text feels, specifically because he discusses algorithms, stored programs, and the mechanical limits of computation. While his contemporaries largely built purely mathematical and logical frameworks, Turing uniquely tied computation theory directly to the abstraction of machines executing stored programs. Because physical hardware capable of executing stored memory programs had not yet been invented, this explicit architectural grounding makes Turing's work remarkably prescient. Still, Turing could not formally connect the Turing Machine to modern architectures, simply because those architectures did not yet exist. Here, by modern, I refer to architectures utilizing random access system memory, dedicated instruction fetch streams with dynamic branching, and discrete processing units. Though Charles Babbage's 1842 Analytical Engine touched on these concepts, they would wait until the 1940s to reemerge. The practical engineering context of 1936 was limited to calculating machines programmed via patch panels. Hence, for example, there is no explanation in his paper as to why a von Neumann architecture machine (1945) running a program would exhibit the computation theoretic results derived from a computation theory based on the Turing Machine (1936).

@@ -172,7 +172,7 @@

The classic text by Hamacher, Vranesic, and Zaky carefully defines the organizational level as sitting between architecture and implementation V. Carl Hamacher, Zvonko G. Vranesic, and Safwat G. Zaky, Computer Organization, 5th ed. (New York: McGraw Hill, 2002).. - Organization is the register transfer level description of the machine, which includes internal buses, external buses and the state machines that implement the protocols used, control units, interrupt structures, and ALU layout. Crucially, it is at this level that decisions regarding instruction level parallelism are made, such as whether the processor will employ a scalar, superscalar, or VLIW design, the depth of its execution pipelines, the use of out of order execution, branch prediction strategies, and the specific hierarchy of hardware caches. It dictates the logical arrangement of hardware and the procedures that force the data to flow to satisfy the architectural constraints. Organization is sometimes called micro architecture, and it is made by a design architect. + Organization is the register transfer level description of the machine, which includes internal buses, external buses and the state machines that implement the protocols used, control units, interrupt structures, and ALU layout. Crucially, it is at this level that decisions regarding instruction level parallelism are made, such as whether the processor will employ a scalar, superscalar, or VLIW design, the depth of its execution pipelines, the use of out of order execution, branch prediction strategies, and the specific hierarchy of hardware caches. It dictates the logical arrangement of hardware and the procedures that force the data to flow to satisfy the architectural constraints. Organization is sometimes called micro architecture, and it is made by a design architect.

@@ -202,7 +202,7 @@

- The common understanding of the word 'architecture' is what Hamacher and Zaky call an organization. For example, even the most experienced of architects will say things like a microprocessor has a "superscalar architecture", though whether a processor is a scalar, superscalar, or VLIW machine is clearly a question of computer organization. + The common understanding of the word 'architecture' is what Hamacher and Zaky call an organization. For example, even the most experienced of architects will say things like a microprocessor has a "superscalar architecture", though whether a processor is a scalar, superscalar, or VLIW machine is clearly a question of computer organization.

@@ -234,7 +234,7 @@

Suppose we are interested in a given Turing Machine m_i where the machine will potentially be run after being given any one of a number of input tapes x_{i,j}, and for each of those inputs the same tape with the results written will be r_{i,j}, then we notate this as:

- + m_i(x_{i,j}) = r_{i,j} @@ -286,7 +286,7 @@

then we can say without qualification that T is a same results transform. Though still implied are the sets of machines, tapes, and questions.

- +

Definition of the computation theoretic consequential/inconsequential transform property

@@ -363,7 +363,7 @@

  • q_0: The initial state, a member of Q, in which the finite control is found.
    • - +
  • F: The set of final or accepting states, a subset of Q.
    • @@ -375,7 +375,7 @@

    This machine makes use of a single ended tape. If a computation specifies a two way infinite tape, it can be emulated by interleaving the addresses: assigning odd addressed cells to represent the right going half, and even addressed cells to represent the left going half. This emulation requires taking two steps instead of one to advance in a given logical direction. When analyzing the time complexity of an algorithm, this overhead doubles the constant on the linear term, leaving the asymptotic order of complexity entirely unchanged. The outcomes of decider programs are unaffected. Therefore, utilizing a single ended tape is a computation theoretic inconsequential variation of the two way tape machine.

    - +

    Hopcroft and Ullman explain a step of the machine by showing a representation of the tape with the state variable melded in to the left of the currently scanned symbol. Suppose δ(q, X_i) = (p, Y, L); i.e., the next move is leftward. Then,

    @@ -408,7 +408,7 @@ q1: ' ' : {L: done} [0, 1]: {R: q_scan} - + # Scan to the rightmost digit and place the EOM terminator 'E' q_scan: [0, 1]: R @@ -453,56 +453,56 @@

    The following trace demonstrates the reversal of the string "110" using the same head embedded in the tape diagram as was used above, with a small variation. Here the head position is indicated using a bullet character, while the current state is listed in the left column. The empty symbol prints as a space. If you align the first line at the top of your window and scroll down, the execution plays out like an animation.

    - q_init • 1 1 0 - q1 •1 1 0 - q_scan 1•1 0 - q_scan 1 1•0 - q_scan 1 1 0• - q2 1 1•0 E - s0 1 1 *•E - s0 1 1 * E• - q3 1 1 *•E 0 - q3 1 1•* E 0 - q3 1•1 * E 0 - q3 •1 1 * E 0 - q3 • 1 1 * E 0 - q4 •1 1 * E 0 - q4 1•1 * E 0 - q4 1 1•* E 0 - q2 1•1 * E 0 - s1 1 *•* E 0 - s1 1 * *•E 0 - s1 1 * * E•0 - s1 1 * * E 0• - q3 1 * * E•0 1 - q3 1 * *•E 0 1 - q3 1 *•* E 0 1 - q3 1•* * E 0 1 - q3 •1 * * E 0 1 - q3 • 1 * * E 0 1 - q4 •1 * * E 0 1 - q4 1•* * E 0 1 - q2 •1 * * E 0 1 - s1 *•* * E 0 1 - s1 * *•* E 0 1 - s1 * * *•E 0 1 - s1 * * * E•0 1 - s1 * * * E 0•1 - s1 * * * E 0 1• - q3 * * * E 0•1 1 - q3 * * * E•0 1 1 - q3 * * *•E 0 1 1 - q3 * *•* E 0 1 1 - q3 *•* * E 0 1 1 - q3 •* * * E 0 1 1 - q3 • * * * E 0 1 1 - q4 •* * * E 0 1 1 - q2 • * * * E 0 1 1 - q5 •* * * E 0 1 1 - q5 •* * E 0 1 1 - q5 •* E 0 1 1 - q5 •E 0 1 1 - q5 •0 1 1 + q_init • 1 1 0 + q1 •1 1 0 + q_scan 1•1 0 + q_scan 1 1•0 + q_scan 1 1 0• + q2 1 1•0 E + s0 1 1 *•E + s0 1 1 * E• + q3 1 1 *•E 0 + q3 1 1•* E 0 + q3 1•1 * E 0 + q3 •1 1 * E 0 + q3 • 1 1 * E 0 + q4 •1 1 * E 0 + q4 1•1 * E 0 + q4 1 1•* E 0 + q2 1•1 * E 0 + s1 1 *•* E 0 + s1 1 * *•E 0 + s1 1 * * E•0 + s1 1 * * E 0• + q3 1 * * E•0 1 + q3 1 * *•E 0 1 + q3 1 *•* E 0 1 + q3 1•* * E 0 1 + q3 •1 * * E 0 1 + q3 • 1 * * E 0 1 + q4 •1 * * E 0 1 + q4 1•* * E 0 1 + q2 •1 * * E 0 1 + s1 *•* * E 0 1 + s1 * *•* E 0 1 + s1 * * *•E 0 1 + s1 * * * E•0 1 + s1 * * * E 0•1 + s1 * * * E 0 1• + q3 * * * E 0•1 1 + q3 * * * E•0 1 1 + q3 * * *•E 0 1 1 + q3 * *•* E 0 1 1 + q3 *•* * E 0 1 1 + q3 •* * * E 0 1 1 + q3 • * * * E 0 1 1 + q4 •* * * E 0 1 1 + q2 • * * * E 0 1 1 + q5 •* * * E 0 1 1 + q5 •* * E 0 1 1 + q5 •* E 0 1 1 + q5 •E 0 1 1 + q5 •0 1 1 done • 0 1 1 @@ -510,10 +510,10 @@
    - \text{steps} = - \begin{cases} - 2 & \text{if } n = 0 \\ - 3n^2 + 6n + 5 & \text{if } n \ge 1 + \text{steps} = + \begin{cases} + 2 & \text{if } n = 0 \\ + 3n^2 + 6n + 5 & \text{if } n \ge 1 \end{cases}
    @@ -565,9 +565,9 @@ def read(c): - if is_empty(c): + if is_empty(c): return 'empty' - else: + else: return c.get() @@ -602,7 +602,7 @@

    Firstly note that excluding SP from Σ does not prevent a Turing machine from writing SP to a tape to be used as a message. If a message writing machine wants to write an SP to the tape, it merely writes a different symbol then erases it.

    Secondly, once it is realized that SP symbols can be written to tape as messages, the very reason of excluding it from Γ, to guarantee that received messages are parsable, is lost. A message authoring machine could, for example, happily output a variable length array of strings while using an arbitrary number of empty symbols to separate the elements. A receiving machine could then not know how many elements it should try to recover, or when to say a string of SP symbols is sufficiently long to not be considered a separator. Nothing in the Turing Machine definition prevents this.

    - +

    Furthermore, the Universal Turing Machine can act as the aforementioned higher authority. In this case, Turing Machines, and sometimes their tapes, are written to a Universal Turing Machine's tape. Consequently, it is not only possible to want to terminate multiple strings in series, as mentioned in the prior paragraph; the termination issue itself is embedded in proofs such as the Halting Problem.

    A common technique programmers use for embedding strings with terminators within other strings is to embed escape characters. This is another in-band protocol, and it is inefficient. The escape sequences grow exponentially with nesting levels. Also, such strings with embedded escape sequences cannot be interpreted without knowledge of the intended nesting level of the string author, which requires the interpreter of the string to know the author's intentions.

    @@ -723,9 +723,9 @@

    q: is the current state of the machine.

    - +

    d: is the data register.

    - +

    g: is the gate register.

    @@ -855,13 +855,13 @@ # Phase 1: Scan right to EOM and initialize the EOR marker. Q·initial: λ: read_g - δ: + δ: (EOM: Q·Setup_EOR) Q·Search_EOM_0 Q·Search_EOM_0: λ: right - δ: + δ: Q·initial Q·Setup_EOR: @@ -986,7 +986,7 @@

    The number of states is constant at 24 independent of how much data is to be reversed. No arc refers to a payload value.

    -

    The form of this diagram shows a lead in, a long loop, and a tail leading to done. This is suggestive of code followed by a while loop that breaks out and then further code completes the program.

    +

    The form of this diagram shows a lead in, a long loop, and a tail leading to done. This is suggestive of code followed by a while loop that breaks out and then further code completes the program.

    void TTCA·reverse_string() { @@ -1003,7 +1003,7 @@ while(g == EOM || g == SP){ status(); // Termination: Short-circuit for empty string - if(g == on_leftmost) return; + if(g == on_leftmost) return; left(); read_g(); } @@ -1046,10 +1046,10 @@
    - \text{steps} = - \begin{cases} - 7 & \text{if } n = 0 \\ - 4.5n^2 + 11.5n + 5 & \text{if } n \ge 1 + \text{steps} = + \begin{cases} + 7 & \text{if } n = 0 \\ + 4.5n^2 + 11.5n + 5 & \text{if } n \ge 1 \end{cases}
    @@ -1067,7 +1067,7 @@ # Phase 1: Both heads scan right to the EOM pivot Q·initial: λ: read_g(0) - δ: + δ: (EOM: Q·Check_Empty) Q·Scan_Right_0 @@ -1163,10 +1163,10 @@
    - \text{steps} = - \begin{cases} - 4 & \text{if } n = 0 \\ - 9n + 4 & \text{if } n \ge 1 + \text{steps} = + \begin{cases} + 4 & \text{if } n = 0 \\ + 9n + 4 & \text{if } n \ge 1 \end{cases}
    @@ -1228,20 +1228,22 @@
    Figure 1 A Turing Machine
    -

    The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few variations. The architecture has no 'unspecified' symbol. Rather an actual value is transacted. The controller is practical to implement, and it was specified in terms of tables, which can be implemented. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. As this is a constant time operation, it is computation theoretic inconsequential.

    +

    The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few modifications. The architecture has no 'unspecified' symbol. Rather, an actual value is transacted. Now that data and control have been separated, the controller is practical to implement, and even more so because it was defined in terms of tables that can be built in hardware. As the status command returns the cell type, it will in its current form be able to return 'rightmost', so that the right end of the tape can be detected. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. This could be signaled either by a panel light that illuminates upon the machine finding a rightmost status, or by the program printing a message on the console teletype. As this is a constant time operation, it is computation theoretic inconsequential.

    -

    Because a Turing Machine can only reach another cell further out on the tape by stepping to it, space complexity and time complexity are related. A program that runs for ten steps can consume at most ten cells of tape. However, if that program merely bounces between two cells, it will require less than that—precisely two cells. A program that counts the number of characters on its input tape using Arabic notation will execute in asymptotically linear time, as demonstrated later in the section analyzing the increment operation. Its working footprint, however, will be logarithmic in space complexity, because that is how fast an Arabic representation grows with a count.

    +

    Because a Turing Machine can only reach another cell further out on the tape by stepping to it, space complexity and time complexity are related. A program that runs for ten steps can consume at most ten cells of tape. However, if that program merely bounces between two cells, it will require less space, precisely two cells. As another example, a program that counts the number of characters on its input tape using Arabic notation will execute in asymptotically linear time, as demonstrated later in the section analyzing the increment operation. Its working footprint, however, will be logarithmic in space complexity, because that is how fast an Arabic representation grows with a count.

    -

    If a program ran at human operator speed, it would be quite slow, likely so much so that the operator waiting for the results would abandon the process. This highlights another attribute of good programs: utility. It also demonstrates one of the limitations of computation theoretic analysis. Nevertheless, formal analysis retains an important purpose. The execution time of an exponential time program explodes relative to the length of the input, quickly requiring more time than the universe has existed. Computation theory does not instruct upon wall-clock time; rather, it describes behavior against increasing input lengths for worst-case operands, which has important implications for wall-clock time.

    +

    If a program executed at the speed of a human operator, the operator would likely abandon the process before it finished. This highlights a necessary attribute of good software: utility. It also exposes a limitation of pure computation theory, which abstracts away physical time. Nevertheless, formal analysis remains a necessity. Consider an exponential-time program processing worst-case operands: its execution time explodes relative to input length, rapidly exceeding the age of the universe. In such extremes, empirical wall-clock measurement becomes superfluous. Computation theory does not calculate wall-clock durations; rather, it classifies a program's behavior, which has implications for wall-clock time.

    The same can be said for space complexity. Suppose a program doubled its memory footprint each time its input string increased by one. If an individual proton could hold one bit of memory, say via its spin, an input increase of merely 270 characters for such a program would exhaust all the protons in the universe. Allocating a cell of space requires the machine to take a step, so time complexity is at least equal to space complexity. If a computer ran at 10 GHz and a step required 10^{-10} seconds, this same extension would require 6 \times 10^{63} years. For perspective, the universe is approximately 1.4 \times 10^{10} years old.

    -

    This book provides the transformational steps needed to go from the Turing Machine to real machines, and one objective is to recover some correspondence between the machine steps of the model and the wall-clock time the machine takes to run. Given this, the system operator changing tapes creates a step that is disproportionately longer than the other steps, a factor that requires architectural mediation, but will not go away. For example, this structural penalty resurfaces in the form of cache misses causing a machine to reach into system memory, or worse, page faults, requiring a machine to go back to disk. +

    This book provides the transformational steps needed to go from the Turing Machine to real machines, and one objective is to recover some correspondence between the machine steps of the model and the wall-clock time the machine takes to run. Given this, the system operator changing tapes creates a step that is disproportionately longer than the other steps, a factor that requires architectural mediation, but will always remain. For example, this structural penalty resurfaces in the form of cache misses causing a machine to reach into system memory, or worse, page faults, requiring a machine to go back to disk.

    As a possible practical solution, note that if the program does not exhaust the current tape, the operator will never be called. How much tape is required to ensure this? An analyst could choose worst-case operands and measure the footprint when the program runs. At first, this appears to be the familiar 'my number is bigger than your number, I'll tell you mine after you tell me yours' game, which can be viewed as the definition for the countable infinity. However, there is a loophole. Running the system once with the worst-case operands to establish time and space ceilings guarantees the program can be allocated sufficient resources later for other operands. This is a practical approach, provided the program is a workhorse utility rather than an algorithm searching for a solution to an unsolved problem that only needs to run once.

    -

    Suppose a controller is not analyzed to determine its computation theoretic complexity, or even tested against worst-case inputs, but is instead run with random or everyday input to gather performance measurements. This process is called profiling. After many runs, a programmer might surmise the behavioral limits of the program. However, many programs are neither linear systems nor smooth functions. With a different set of inputs than those used for profiling, perhaps even values adjacent to prior inputs, the program behavior can shift drastically. Take, for example, the Pentium divider. It did not matter how many millions of times the result was accurate; the fact remains that customers later found an input that yielded wildly inaccurate results. Only by elevating the analysis to the structural logic of the code can such an eventuality be categorically ruled out. This is why the K5 transcendental function development project included a proof writing phase, see Thomas Walker Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, "The K5 Transcendental Functions," Proceedings of the 12th IEEE Symposium on Computer Arithmetic, 1995. DOI: 10.1109/ARITH.1995.465368.

    +

    Another practical solution, one that also applies to the first run of the program, is to analyze the logic to compute the time per step and extrapolate the total execution time. This is not universally possible; for some programs, tracing a path through the execution logic is as computationally complex as running the program itself, taking us back to the analysis in the prior paragraph. However, this boundary does not apply to all systems. Consider the previously mentioned examples of the ten step machine, the machine bouncing between two cells, and the Arabic counting machine.

    + +

    Suppose a controller is not analyzed to determine its computation theoretic complexity, or even tested against worst-case inputs, but is instead run with random or everyday input to gather performance measurements. This process is called profiling. After many runs, a programmer might surmise the behavioral limits of the program. However, many programs are neither linear systems nor smooth functions. With a different set of inputs than those used for profiling, perhaps even values adjacent to prior inputs, the program behavior can shift drastically. Consider the Pentium divider. It did not matter how many millions of times the result was accurate; the fact remains that customers later found an input that yielded wildly inaccurate results. Only by elevating the analysis to the structural logic of the code can such an eventuality from an erroneous algorithm be categorically ruled out. This is why the K5 transcendental function development project included a proof writing phase; see Thomas Walker Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, "The K5 Transcendental Functions," Proceedings of the 12th IEEE Symposium on Computer Arithmetic, 1995. DOI: 10.1109/ARITH.1995.465368.

    Head unit, HU

    @@ -1254,7 +1256,7 @@

    One or more head units are plugged into the TTU, which is described in the next section. Commands are only sent to the head unit when a tape is mounted on the TTU, and they are sent by the TTU. The machine at large does not have an interface to the HU.

    - +

    The status command returns the name of the cell type of the cell the head is on. The head controller communicates with other components of the machine to ascertain the status, which is one of:

      @@ -1264,7 +1266,7 @@
    1. island
    -

    A status of rightmost or island would never be returned for a computation theoretic Turing Machine tape, but it can be for an area of a tape, and such an area can be a virtual tape, as is described in the later section on Area.

    +

    A status of rightmost or island would never be returned for a computation theoretic Turing Machine tape, but it can be for an area of a tape, and such an area can be an abstract virtual tape, as is described in the later section on Area.

    Tape transport unit, TTU

    @@ -1278,7 +1280,7 @@
  • a single symbol FIFO command buffer, written by the programmed controller, acted upon immediately by the TTU
    • -

    The TTU interfaces with the executor, which in turn contains the customer programmed control unit, the CPCU. The executor is single-threaded and issues commands to the TTU:

    +

    The TTU interfaces with the executor, which in turn gates the flow of data through the machine. The executor controls the clock and reset lines, and through this supervises the customer programmed control unit, the CPCU. This two-layer control system is single-threaded and issues the following commands to each selected TTU:

    1. read head → σ
      2. @@ -1292,50 +1294,73 @@

      The customer programmed control unit, CPCU

      -

      The controller is programmed via patch panel. The panel would look something like this:

      +

      The customer programmed control unit, CPCU

      + +

      The controller is programmed via patch panels. The panels would look something like what is shown in the following ASCII art blocks. Note that {*} indicates an illuminated indicator light, whereas { } is not illuminated. [/] represents an open toggle switch, while [\] is a closed one. ( ) represents a hole for a banana plug. Each patch cord has a banana plug on each end. The patch cords should not cross between panels.

      - + 
      -=================================================================
-               TTCA PROGRAMMABLE STATE CONTROLLER
-=================================================================
-
-[ CONTROL PANEL ] 
-(o) POWER  [/] Toggle     
-( ) RUN    [/] Toggle       ( ) RESET [Btn]    (*) STEP [Btn]
-
------------------------------------------------------------------
-[ GATE ]             [ STATE INDICATOR LIGHTS ]
-[ IND. ]             S0    S1    S2    S3    S4    S5
-                     ( )   ( )   (*)   ( )   ( )   ( )
-                      |     |     |     |     |     |
-                      V     V     V     V     V     V
+                            [ CONTROL PANEL ]
+                +-----------------------------------------+
+                | {o} POWER  [/] Toggle ( ) RESET [Btn]   |
+                | { } RUN    [/] Toggle (*) STEP [Btn]    |
+                +-----------------------------------------+
+
      + + 
      +                              [ State Transition Table ]
+                         +-----------------------------------+
+           current state | S0    S1    S2    S3    S4    S5  |
+        indicator lights | {*}   { }   { }   { }   { }   { } |
+         halting toggles | [/]   [/]   [/]   [/]   [/]   [/] |
+                         +-----------------------------------+
+      { } g0 (Empty)  g0 | ( )   ( )   ( )   ( )   ( )   ( ) |
+      {*} g1 (Sym 0)  g1 | ( )   ( )   ( )   ( )   ( )   ( ) |
+      { } g2 (Sym 1)  g2 | ( )   ( )   ( )   ( )   ( )   ( ) |
+      { } g3 (Mark *) g3 | ( )   ( )   ( )   ( )   ( )   ( ) |
+      { } g4          g4 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                         |                                   |
+       destination state | ( )   ( )   ( )   ( )   ( )   ( ) |
+                         | ( )   ( )   ( )   ( )   ( )   ( ) |
+                         | ( )   ( )   ( )   ( )   ( )   ( ) |
+                         |                                   |
+       default transition| ( )   ( )   ( )   ( )   ( )   ( ) |
+       global transition |               ( )                 |
+                         +-----------------------------------+
+
      + + 
      +                                [ Action ]
                    +-----------------------------------+
-( ) g0 (Empty)  g0 | ( )   ( )   ( )   ( )   ( )   ( ) |
-(*) g1 (Sym 0)  g1 | ( )   ( )   ( )   ( )   ( )   ( ) |
-( ) g2 (Sym 1)  g2 | ( )   ( )   (•)===╗ ( )   ( )   ( ) |
-( ) g3 (Mark *) g3 | ( )   ( )   ( )   ║ ( )   ( )   ( ) |
-( ) g4          g4 | ( )   ( )   ( )   ║ ( )   ( )   ( ) |
-                   +-------------------║---------------+
-                                       ║
-                     [ DESTINATION STATE ROWS ]
-                     S0    S1    S2    S3    S4    S5
-                D1 | ( )   ( )   ( )   (•)   ( )   ( ) |
-                D2 | ( )   ( )   ( )   ( )   ( )   ( ) |
-                D3 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                   | S0    S1    S2    S3    S4    S5  |
+               Src | ( )   ( )   ( )   ( )   ( )   ( ) |
+                   +-----------------------------------+
+          right    | ( )   ( )   ( )   ( )   ( )   ( ) |
+          left     | ( )   ( )   ( )   ( )   ( )   ( ) |
+          read_g   | ( )   ( )   ( )   ( )   ( )   ( ) |
+          read_d   | ( )   ( )   ( )   ( )   ( )   ( ) |
+          write_g  | ( )   ( )   ( )   ( )   ( )   ( ) |
+          write_d  | ( )   ( )   ( )   ( )   ( )   ( ) |
+          write_σ  | ( )   ( )   ( )   ( )   ( )   ( ) |
                    +-----------------------------------+
-
-                     [ DEFAULT TRANSITIONS ]
-                     S0    S1    S2    S3    S4    S5
-      STATE DFLT   | ( )   ( )   ( )   ( )   ( )   ( ) |
-
-      GLOBAL DFLT  |              ( )                  |
-=================================================================
      -       + + 
      +                        [ Sigma Select for write_σ ]
+                   +-----------------------------------+
+                   | S0    S1    S2    S3    S4    S5  |
+               Src | ( )   ( )   ( )   ( )   ( )   ( ) |
+                   +-----------------------------------+
+                g0 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                g1 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                g2 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                g3 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                g4 | ( )   ( )   ( )   ( )   ( )   ( ) |
+                   +-----------------------------------+
+
      + +

      The top section has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Immediately to the left of the two toggles are indicator lights. To the right of the toggle switches are two push buttons. One is for reset, which sends the machine back to state S_0, and the other is for stepping the machine when it is in single-step mode.

      -

      The top section has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Just to the left of the two toggles are indicator lights. To the right of the toggle switches are two push buttons. One is for reset, which sends the machine back to state S_0, and the other is for stepping the machine when it is in single-step mode.

      -

      The second section is the transition condition panel. It is a rectangular matrix of holes that fit the banana plug ends of a patch cord. Each column corresponds to a current state, and each row corresponds to a gate symbol.

      Below the transition condition panel is the destination state panel. All three rows of this panel are functionally identical; they merely provide physical space so multiple patch cords can be plugged into a single state column.

      @@ -1344,8 +1369,7 @@

      To program the controller, the programmer connects the patch cords. Shown in the diagram is a patch cord routing from the (S_2, g_2) intersection to S_3. This physically realizes a state transition arc for the controller. If the active gating value has no patch cord plugged in, the machine instead uses the state default transition. For a state default transition, a patch cord is plugged into the column for the current state on the default transition panel and routed to the desired next state. Finally, if no patch cord is plugged in that would otherwise define the next state, the global default patch cord is followed.

      -

      Not shown in this diagram is a row of toggle switches, one per state; if flipped on, the corresponding state becomes a halting state. Also omitted is the action selection panel. It is another rectangular matrix, with rows for actions and columns for the states, allowing each state to be assigned to a specific machine action. Note that this describes the control panel for a single-head TTU machine.

      - +

      Not shown in this diagram is a row of toggle switches, one per state; if flipped on, the corresponding state becomes a halting state. Also omitted is the action selection panel. It is another rectangular matrix, with rows for actions and columns for the states, allowing each state to be assigned to a specific machine action. Note that this describes the control panel for a single-head, single-TTU machine. Additional patch options would be required to add a TTU device specifier and a head specifier within each TTU.

      The machine block diagram

      @@ -1354,294 +1378,84 @@
      Figure TTCA block diagram
      -

      Components

      +

      Components

        -
      1. Executor
        2. -
          -
        1. clock
          2. -
        2. Control Panel
          3. +
        3. Executor
            -
          1. Power Switch
            2. -
          2. Single Step Switch
            3. -
          3. Reset Button
            4. -
          4. Single Step Button
            5. +
          5. Control Panel +
              +
            1. Power Switch
              2. +
            2. Single Step Switch
              3. +
            3. Reset Button
              4. +
            4. Single Step Button
              5. +
            +
            6. +
          6. halt state switch bank
            7. +
          7. clock and distribution lines (clk)
            8. +
          8. reset distribution lines
          -
        - +
      2. g register
      3. status bus
        4. -
      4. Status Decoder
        5. - +
      5. Gate Decoder
      6. d register
      7. data bus
        8. - -
      8. Customer Programmed Control Unit, CPCU
        9. -
          -
        1. current state register, q
          2. -
        2. next state table
          3. -
        3. action table
          4. -
        4. halt state decoder and switches
          5. -
        - -
      - -

      The Executor provides the ultimate control of the machine, telling registers when to sample or latch, enabling bus drivers, and distributing the clock and reset signals. These control signals are not shown in this block diagram (it is not a schematic).

      - -

      There are two registers in the register file. The d register, holds data values that are being carried. The d register has no path to the customer programmed controller. The g register holds the status value used for gating the controller. -

      - -

      The symbols used for status and gating the programmed controller occur within an enumeration. Each is given a value that corresponds to its the row index on the control panel. The value on the status bus then is latched by the g register and goes to a decoder which has one output line per symbol. Decoding the status then results in a one hot value sent to the state transition logic for gating to the next state. Due to the enumeration, the decoder displaces the need for a bank of comparators each checking for a distinct symbol on the status bus.

      - -

      The halt state detection works in a similar manner. The current state register is also a one hot encoding, with a bit per state. A wire from each bit goes to the executor where it meets the bank of halt switches. the output of which is wire OR'ed together to create the halt signal. Thus for halt to be asserted, the given state must be turned on in the switch bank. -

      - -

      Upon reset the current state register all of the machine registers are cleared to zeros. Also, the power on switch has a capacitor timer that holds reset for a safe amount of time while the machine comes up.

      - -

      Timing

      - -

      A magnetic tape head reads when the tape is moving, so ironically it is like the emacs cursor. The read will occur when the machine steps and the data will be waiting in the data buffer for a read command. The head will wait at the other side of the cell. Unlike the theoretical tape, there is interstitial space between the cells where the head can wait for the next command, then swipe further right. In a real machine blocks of cells will always be read, and the buffer will be much deeper.

      - -

      On a read for the g register

      - -

      So on the falling edge of the clock, the state is latched. State signal ripples through the action table. As the q register is stored one hot, this happens very quickly. The command arrives at the TTU, and is decoded. The decoder can be avoided by having the action table send the already decoded value.

      - -

      As the read is to be used for control, i.e. to cause a state transition, the bus control signals will be setup such that the status register of the TTU is sent through the g register, through the g value decoder, and in to the customer programmed controller. There the one hot value will pass through a patch cord, destined to be latched at the next falling clock edge.

      - -

      On the rising edge of the clock, the gate value is latched. The flip flops that drive the gate lights are sampled. This assures that the next state transition signals are held stable ... - -

      Stored Program Control

      - -

      Configuring and debugging a patch panel is a cumbersome task. The patch panel can instead be programmed with an interpreter, and then the interpreter can interpret the program found as data on the tape. This is then a Universal Turing Machine. The program being interpreted then can call out TTCU commands directly, as functions in software. In fact, the stored program is so much easier to use, that some models of our machine will have the patch cords inserted at the factory with the patch panel placed inside the cabinet. -

      - -

      The next chapter discusses the stored program langauge.

      - -

      Here is an example customer defined programmed controller for incrementing a unary number:

      - - - Data alphabet: {s} - States: {0, 1, 2, 3, 4} - Initial state: 0 - Halt state: 3 - Error state: 4 - - State dictionary: - { - 0: n op - s -> 1 - □ -> 2 - 1: step_right - s -> 1 - □ -> 2 - 2: write(s) - * -> 3 - } - - Default next state table: { - status:left-of-leftmost -> 4 - } - - - - - - - - - - - - - - - - - - - - - - -

      - The distinct empty symbol can be any symbol that is excluded from the alphabet. Only instances of alphabet symbols or the empty symbol are permitted to be written to the tape. -

      - -

      - Intuitively, a person might consider that the alphabet symbols are useful while the empty symbol is merely taking up space while waiting to be displaced, in the same manner that a person considers a bookshelf to be empty rather than being full of air. (And if a person puts a bookshelf underwater, is it still empty, or is it full of water?). -

      - -

      - If a physical machine receives power without the reset signal being held, it can land in an illegal state. This is hazardous as the machine might become permanently stuck in a configuration that ignores subsequent reset commands, it might operate unpredictably, or it might even suffer physical hardware damage. To avoid these outcomes, systems are designed to hold the reset line active while the power comes up. Asserting the reset signal, rather than recycling power, is what actually causes a machine to land in a known initial state. Consequently, we must include a reset feature. -

      - -

      - This design assumes that when reset is released, that the machine immediately starts running. This is fine for our purposes, but surely the deluxe model would have a separate 'go' button and the associated logic. -

      - -

      - The tape transport unit, TTU, handles mounting, unmounting, reading, writing, and moving, the tape. In this volume we will talk about stepping the head. This should be interpreted in a relative sense, as a real TTU will move the tape rather than the head. Our machine is designed such that the customer can plug in more than one TTU unit. Each unit has its own read buffer, status buffer, and head. A tape can be mounted or unmounted from each unit. At the election of the operator, the tape can be unmounted from one TTU, shelved perhaps, then unshelved and mounted back on the any TTU, the same one, a different one on the same machine, or a TTU on another machine. -

      - -

      - The constant executor should not be conflated with the Turing Machine program. For a microcode controlled machine, the procedure will be found in microcode memory, and it will be executed as though a program. Each line of the procedure, when read, results in a set of bits being connected to the machine's control lines. Some of those control lines will control what the procedure does, and some will extend out into the data path and be used to configure execution units and gate data on to busses. -

      - -

      - For a hardwired machine, the operation program will be expressed with logic gates and flip flops (single bit memory registers). Whether a machine is microcode controlled, or hardware controlled is a question of implementation. The values on the control lines remain the same independent of those implementation decisions, so those decisions are inconsequential to our architecture discussion. -

      - -

      - The Turing Machine architecture specifies an infinite tape, which can neither be implemented, nor realized. We will introduce a computationally inconsequential modification in a later chapter that causes the tape to be finite. -

      - - -

      Machine

      - -

      The immutable structural components:

      -
        -
      1. a read only empty symbol that is distinct from any symbol in the data alphabet. The examples in this document use the symbol '□'
        2. -
      2. a read only control alphabet for this base model, consisting of the one symbol leftmost
        3. -
      3. a read writable current state reference variable, which points into the custom predefined program controller
        4. -
      4. a fixed hardware halt state comparator
        5. -
      5. a tape transport unit, TTU, from which tapes can be mounted and unmounted. Multiple TTUs can be plugged in. Each TTU contains: +
      6. CPCU
          -
        1. a read/write head
          2. -
        2. a single symbol FIFO read data buffer, written by the TTU, read by the programmable controller
          3. -
        3. a single symbol FIFO status buffer, written by the TTU,, read by the programmable controller
          4. -
        4. a single symbol FIFO command buffer, written by the programmed controller, acted upon immediately by the TTU.
          5. +
        5. one-hot q register
          6. +
        6. next state table
          7. +
        7. action table
      -

      The fixed logic internal to the machine:

      -
        -
      1. a constant executor where each step of the procedure can be referenced by number
        2. -
      2. a read/writable/incrementable executor step counter
        3. -
      3. a reset button that activates logic that initializes the machine
        4. -
      4. a read only clock to synchronize control and to cause counting until the halt state is reached
        5. -
      +

      This is a top-level block diagram, not a schematic. It is of sufficient detail to express the organization of the machine and to guide the implementation. Not shown are the clock lines going to all clocked registers, and the reset line going to all registers. Missing also are the details of the executor control, and details of the TTU control.

      -

      Accessories:

      -
        -
      1. tapes, as described in a prior section
        2. -
      2. a Universal Turing Machine package, consisting of the Universal Turing Machine programmable controller and auxiliary alphabet, which comes with tapes containing example programs
        3. -
      +

      The executor provides the ultimate control of the machine, telling registers when to sample or latch, enabling bus drivers, and distributing the clock and reset signals.

      -

      Each highlighted term is a short name for the associated item.

      +

      There are two registers in the register file. The d register holds data values that are being carried. The d register has no path to the customer programmed controller. The g register holds the status value used for gating the controller.

      +

      The symbols used for status and gating the programmed controller occur within an enumeration. Each is given a value that corresponds to its row index on the control panel. The value on the status bus is then latched by the g register and goes to a decoder which has one output line per symbol. Decoding the status then results in a one-hot value sent to the state transition logic for gating to the next state. Due to the enumeration, the decoder displaces the need for a bank of comparators, each comparator checking for a distinct symbol on the status bus.

      +

      The current state register is a one-hot encoding, with a bit per state. A wire from each bit goes to the executor where it meets the bank of halt switches, the outputs of which are all wire-ORed together to create the halt signal. Thus, for halt to be asserted, the given state must be turned on in the switch bank.

      -

      Operation logic

      +

      Upon reset, the current state register is set to a one-hot configuration, with the single active bit acting as the state 0 indicator. All other machine registers are cleared to zeros. Also, the power switch has a capacitor timer that holds reset for a safe amount of time while the machine comes up.

      - The following procedure is embodied as further control logic in the Turing Machine. This procedure is fired upon receiving a step pulse. At the time the procedure is entered, the head is stable upon a cell. We list phases so as to avoid any apparent race conditions. This does not dictate to the designers that the clock must have phases, though that isn't excluded either. + If a physical machine receives power without the reset signal being held, it can land in an illegal state. This is hazardous as the machine might become permanently stuck in a configuration that ignores subsequent reset commands, it might operate unpredictably, or it might even suffer physical hardware damage. To avoid these outcomes, systems are designed to hold the reset line active while the power comes up. Asserting the reset signal, rather than recycling power, is what actually causes a machine to land in a known initial state. Consequently, we must include a reset feature.

      - -

      Deterministic (Uniplex) programmed control procedure

      - -

      Upon each step pulse:

      - -

      Phase 1:

      -
        -
      1. read the symbol instance indicated by the head into the read data buffer
        2. -
      - -

      Phase 2:

      -
        -
      1. lookup the current state in the instruction table
        2. -
      2. lookup the current state concatenated with the read data buffer in the next state table
        3. -
      3. lookup the current state in the default next state table
        4. -
      - -

      Phase 3:

      -
        -
      1. if the current state is found in the next state table, use the retrieved value as the next state. Otherwise, if the current state is found in the default next state table, use the default state as the next state. Otherwise, use the error state as the next state.
        2. -
      2. if an instruction was retrieved from the instruction table, the tape transport executes it. Otherwise, the tape transport executes the default 'no-op' instruction.
        3. -
      - -

      Phase 4:

      -
        -
      1. write the next state to the current state register
        2. -
      2. controller remains quiescent waiting for the next step pulse
        3. -
      - - -

      An alternative: stored program and sequencer

      - The Universal Turing Machine, proposed by Alan Turing, introduced a profound architectural inversion: relocating the defining state tables from hardwired logic, or manually configured patch panels, directly onto the tape itself. This enables replacing the custom programmed controller with a fixed controller that derives its behavior dynamically from the tape data. Consequently, a single, immutable hardware architecture can simulate the execution of any conceivable Turing Machine. + This design assumes that when reset is released, the machine immediately starts running. This is fine for our purposes, but surely the deluxe model would have a separate 'go' button and the associated logic.

      - In addition, encoding a machine's control logic as parseable data on tape establishes an ontology of analysis, a framework where a machine can analyze another machine to establish some properties the other machine might have. We say 'some' because at least one limitation has been proven. Alan Turing proved that such an analyst cannot in general determine if said other machine has the property that it would halt for any input when run. + The tape transport unit, TTU, handles mounting, unmounting, reading, writing, and moving the tape. In this volume we will talk about stepping the head. This should be interpreted in a relative sense, as a real TTU will move the tape rather than the head. Our machine is designed such that the customer can plug in more than one TTU. Each unit has its own read buffer, status buffer, and head. A tape can be mounted or unmounted from each unit. At the election of the operator, the tape can be unmounted from one TTU, shelved perhaps, then unshelved and mounted back on any TTU, the same one, a different one on the same machine, or a TTU on another machine.

      - We can optimize this representation. Instead of storing the state tables verbatim, we can list a sequence of instructions directly on the tape. To achieve this, the architecture expands to support two distinct categories of instructions: the physical tape transport instructions we defined previously, and a newly introduced category of control instructions. The programmed controller is then replaced with a fixed hardware controller called a sequencer. + The constant executor should not be conflated with the Customer Programmed Control Unit (the TTCA program). The executor is not programmable by the customer. For a microcode controlled machine, the executor procedure will be found in microcode memory, and it will be executed as though a program. Each line of the procedure, when read, results in a set of bits being connected to the machine's control lines. Some of those control lines will control what the procedure does, and some will extend out into the data path and be used to configure execution units and gate data on to busses.

      - Because the original state tables allowed for non linear execution paths, the instruction sequence on the tape cannot always execute in a straight line. Therefore, the architect must include at least two control instructions: a halt instruction and a test and branch instruction. The sequencer starts at the first instruction in the program, perhaps at the leftmost cell on the tape, and evaluates it. If it is a control instruction, the sequencer acts upon it directly to alter the flow of execution or stop the machine. Otherwise, if it is a physical instruction for the head unit, the sequencer passes it down to the tape transport. + For a hardwired machine, the executor procedure will be expressed with logic gates and flip-flops (single-bit memory registers). Whether a machine is microcode controlled or hardware controlled is a question of implementation. The values on the control lines remain the same independent of those implementation decisions.

      -

      - Because we have not yet derived Natural Numbers or memory addresses in this architecture, a test and branch instruction cannot jump to a numerical address. Instead, it must operate topologically. A topological branch instruction simply commands the sequencer to scan the tape for a specific target symbol, and resume executing instructions from that physical location. -

      +

      Description of a read g command

      -

      - As noted in the prior section, an instruction consists of an instruction code and potentially an argument. There are many choices that can be made in instruction set design. Among those choices, almost all will be inconsequential from a computation theoretic point of view, but almost all will introduce strict efficiency trade offs in physical hardware. -

      +

      A magnetic tape head reads when the tape is moving, so ironically it is like the Emacs cursor. The read will occur when the machine steps and the data will be waiting in the data buffer for a read command. The head will wait at the other side of the cell. Unlike the theoretical tape, there is interstitial space between the cells where the head can wait for the next command, then swipe further right. In a real machine, blocks of cells will always be read, and the buffer will be much deeper.

      +

      The current state latch, q, is open on the falling edge of the clock, and then samples and holds while the clock is high. The gate register, g, is the phase inverse; it is open while the clock is high, and samples and holds while the clock is low.

      -

      Operation logic

      +

      On the rising edge of the clock, the state is latched. The current state signal ripples through the action table. As the q register is stored as a one-hot value, this happens very quickly. Rather than placing commands in the action table, the decoded values of the commands that are needed for control are programmed directly into the table. Among the decoded outputs of the action command is a control signal that enables the opening of the gate register latch.

      -

      - In the prior two sections we discussed the configurable part of the Turing Machine control. Here we complete the picture by describing the fixed portion. -

      +

      A control signal from the decoded command coming from the action table then enables the selected TTU, and if the TTU command is already decoded, a line will select either the TTU read register (for the read_d command) or the selected status register (for the read_g command). Both values are ready to drive the bus when the control signal arrives.

      -

      Setup

      -
        -
      1. select and mount a tape
        2. -
      2. push the reset button
        3. -
      +

      At this time the q latch is enabled and open, so the selected value travels through the latch to a decoder, and then to the state transition table, where it energizes a row, reaches the patch cord, and the signal travels through the patch cord and illuminates the next state bit. This is the critical path that sets the clock period, provided that the TTU controller is not slower.

      -

      Reset

      -
        -
      1. step the head left until an 'left of leftmost' error from the tape transport unit, the head will then be on the leftmost cell
        2. -
      2. hit reset on the programmed controller, or the sequencer, depending on which is being used
        3. -
      3. wait until the release of the reset button
        4. -
      +

      During that time the clock has a falling edge, so the g register latches and holds the gate value. The q register latch opens, waiting for the critical path signal to resolve. It has the remaining low period of the clock to do so, giving it one full clock cycle to resolve.

      -

      Main:

      -
        -
      1. evaluate the value of the reset line coming from the reset button
        2. -
      2. if the reset line is true, execute the Reset procedure
        3. -
      3. if the reset line is false, evaluate the halt line coming from the comparator
        4. -
      4. if the halt line is true, freeze execution until reset is asserted, then return to step 1
        5. -
      5. if the halt line is false, send a step pulse to the programmed controller (or sequencer) on each clock tick
        6. -
      - -

      - A person can read this procedure with the caveat, "if we could realize such a machine, this is what we would do." Later, these directions can be modified and applied to the machine variation that has an expanding tape. -

      - -

      - To start the machine we must first select a tape. Common choices are an empty tape, a tape with data on it the machine is to decide matches a given language pattern, or a tape with a Turing Machine on it to be analyzed. After the tape is selected it is mounted on the Turing Machine, then the reset button is hit. -

      - -

      - After the reset button is released, the machine begins stepping. If the program is a computation, the machine will eventually halt. If the machine eventually halts, then we know the associated program was a computation. Otherwise we do not know. Any amount of time we wait where the machine has not halted, we will not know that it will ever halt. Hence, we cannot in general use 'running a Turing Machine' as a means to determine if a given program is computational. (We could instead try to answer the question 'is it computational' through analysis, but there too, Turing has shown that in general that will not work either.) -

      - -

      Operation logic steps, programmed controller steps, and head steps

      - -

      - In common books and papers about the Turing Machine, a step is defined as one step of the programmed controller, i.e. one pass through the four phase procedure given above. Decider proofs ask if the comparator will match the halt state within a finite number of steps. Time complexity proofs take a formulation of step count to reach the halt state, parameterized against the size of the input, and report the order of the highest term as it is asymptotically dominant. Hence we speak of constant, linear, polynomial, and exponential time complexity algorithms. A similar method of analysis, that of memory usage with step count, parameterized against input size, is used for space complexity. -

      - -

      - For a real machine, the step pulse will be derived from the machine clock. The clock will have a constant period, so there is a constant duration of time that will be the same for each pass through the execution procedure. Thus, if we replace the step count with a count of clock ticks, we will get the same decider and complexity results as we would have from step counts. This fits the definition we have been using for inconsequential. -

      +

      Then the clock rises, and the cycle repeats.

      The TTCA stored program @@ -1691,7 +1505,7 @@

      Instance implementation

      - Within a process, a reference to the factory can be used as a symbol instance, which will cause the factory to become trivial. Making a new instance will merely require copying the factory reference, and there will be nothing in memory that the base factory reference is pointing to. + Within a process, a reference to the factory can be used as a symbol instance, which will cause the factory to become trivial. Making a new instance will merely require copying the factory reference, and there will be nothing in memory that the base factory reference is pointing to.

      @@ -1710,7 +1524,7 @@ As another alternative, each factory can be given a base string, and then make returns a copy of the base string. Here we refer literally to the string as the symbol instance. There is no separate name, and the string data, not the reference to the string, becomes the symbol instance. This is however merely an architectural constraint, under the hood an implementation could use string references as long as it always appears to the programmer that the string value is being used.

      -

      +

      At the time of this writing many machines use 64 bit words. This is equivalent to 8 ASCII characters, while the average size of an identifier is about 5 characters. Hence the approach of using a string as a symbol might not be as inefficient as it seems to be at first. Using strings has advantages. Symbol instances can carry semantic clues for the programmer. There is no hazard of conflating the string instance with the name, as they are the same. Also, a string instance will have integrity across contexts, such as between invocations or when passed between processes (note the section below on crossing context boundaries). A drawback is in cases there is no language support, the strings are typically ad hoc so the guarantee of distinctness becomes merely a contract with the programmer.

      @@ -1733,7 +1547,7 @@

      Copying symbol instances is an integral part of the operation of the Turing machine. Typically the programmed control steps are used as a cost metric for running a program. Such steps integrate operations of copying symbols to and from the tape. Thus from a pure step count perspective the cost of the symbol copy is inconsequential, not due to any behavior of a symbol copy, but rather due the symbol copy being subsumed within the definition of the step.

      - However, this is feels unsatisfactory. Here we are tying to build a bridge from computation theory to architecture, and thus we want a step to be a constant time occurrence at least in the average, or at least approximately. To model the symbol copy time, a symbol could be copied a tranche of bits per step, thus giving the copy a step count. Then, if symbols were to grow in tranche count as a program ran longer, then symbol copy of ever longer symbols would be computationally consequential. + However, this is feels unsatisfactory. Here we are tying to build a bridge from computation theory to architecture, and thus we want a step to be a constant time occurrence at least in the average, or at least approximately. To model the symbol copy time, a symbol could be copied a tranche of bits per step, thus giving the copy a step count. Then, if symbols were to grow in tranche count as a program ran longer, then symbol copy of ever longer symbols would be computationally consequential.

      @@ -1875,7 +1689,7 @@

      The value of a neighbor property is a non-null single reference to a cell. The value of a data property is strictly an instance of an alphabet symbol, or alternatively, an instance of the empty symbol.

      - +

      Tape

      @@ -1930,7 +1744,7 @@

      - An axiomatic proof is then a decider that is built up from subroutine calls to the axioms. We might then quantify over all possible compositions of our subroutines in analysis and ask if it is possible that a contradiction decider would return Y or N. + An axiomatic proof is then a decider that is built up from subroutine calls to the axioms. We might then quantify over all possible compositions of our subroutines in analysis and ask if it is possible that a contradiction decider would return Y or N.

      @@ -2015,7 +1829,7 @@

      - Consider an illustrative example. We start by defining a fundamental language for communicating with the head and tape transport unit. The statements we communicate to our tape transport unit will be explicit physical commands: (step), (left), (read), and (write symbol). In the first order, evaluating these commands physically actuates the tape. + Consider an illustrative example. We start by defining a fundamental language for communicating with the head and tape transport unit. The statements we communicate to our tape transport unit will be explicit physical commands: (step), (left), (read), and (write symbol). In the first order, evaluating these commands physically actuates the tape.

      @@ -2034,7 +1848,7 @@

      Similarly, the AST for the number 3:

      - + (defparameter *three-ast* '(progn @@ -2043,13 +1857,13 @@ (write s) (step) )) - +

      - If we were to dynamically evaluate these ASTs in the first order, the Arabic representation of each number would be physically written in unary code on the tape. + If we were to dynamically evaluate these ASTs in the first order, the Arabic representation of each number would be physically written in unary code on the tape.

      - For the second order difference operation, we compose the ASTs to create a new program. Here we extract the body of the second operand's AST and substitute every (write s) followed by a (step) command with an inverted pair: a (left) command followed by writing the empty symbol (write □). + For the second order difference operation, we compose the ASTs to create a new program. Here we extract the body of the second operand's AST and substitute every (write s) followed by a (step) command with an inverted pair: a (left) command followed by writing the empty symbol (write □).

      @@ -2087,8 +1901,8 @@

      We pass our two natural number ASTs to this composer, and we get as a result a newly synthesized AST.

      - (defparameter - *primitive-five-minus-3-ast* + (defparameter + *primitive-five-minus-3-ast* (primitive-compose-subtract *five-ast* *three-ast*) ) @@ -2099,18 +1913,18 @@ ;; (write s) (step) ;; (write s) (step) ;; (write s) (step) - ;; (left) (write □) - ;; (left) (write □) + ;; (left) (write □) + ;; (left) (write □) ;; (left) (write □) ;; ) - +

      I called this 'primitive' because it is missing the simplification. This sort of simplification is also known as compiler code optimization. Optimizations can be operation specific, or general in nature. Here we will send the primitive composition's body to an analyzer which scans the steps and removes the redundant operations.

      - Because of the purity of the Lisp syntax, we are able to present a remedial simplifier example here. A (step) followed by a (left) annihilate each other, resulting in zero net movement of the tape head. Similarly, on an initially empty tape, a (write s) followed immediately by overwriting with the empty symbol (write □) annihilate each other. + Because of the purity of the Lisp syntax, we are able to present a remedial simplifier example here. A (step) followed by a (left) annihilate each other, resulting in zero net movement of the tape head. Similarly, on an initially empty tape, a (write s) followed immediately by overwriting with the empty symbol (write □) annihilate each other.

      @@ -2157,8 +1971,8 @@

      After giving the difference program to the simplifier, we get:

      - (defparameter - *simplified-five-minus-3-ast* + (defparameter + *simplified-five-minus-3-ast* (simplify-machine *primitive-five-minus-3-ast*) ) @@ -2183,7 +1997,7 @@

      Let us take the multiplicative inverse of the additive identity as an example, AKA division by zero. In the second order, when we divide, say 6/0, the machine will not reduce. It will return a second order value:

      - + (divide 6 0) @@ -2199,7 +2013,7 @@ (multiply 2 (divide 0 0)) - +

      There is no special help here. Hence, (divide 0 0) remains as an error flag.

      @@ -2223,10 +2037,10 @@

      - The difference between adjacent function values in the above sequence is called the first finite difference. The forward first difference is defined as: - \Delta_i = f(t_{i+1}) - f(t_i). - While the backwards first difference is - \Delta_i = f(t_i) - f(t_{i-1}). + The difference between adjacent function values in the above sequence is called the first finite difference. The forward first difference is defined as: + \Delta_i = f(t_{i+1}) - f(t_i). + While the backwards first difference is + \Delta_i = f(t_i) - f(t_{i-1}). If 'forward' or 'backwards' is not specified, then the difference is taken to be 'forward'. Hence, extending a function is identical to adding the first difference. Thus a sequence of function values implies a sequence of first differences.

      @@ -2286,7 +2100,7 @@

      - In order to design for indefinite extension, the Turing Machine tape must retain the function value alongside with its forward differences. Because the second difference is constant higher order differences are all zero. Hence the tape requires a three component vector to hold the differences. + In order to design for indefinite extension, the Turing Machine tape must retain the function value alongside with its forward differences. Because the second difference is constant higher order differences are all zero. Hence the tape requires a three component vector to hold the differences.

      @@ -2374,7 +2188,7 @@

      - Taking successive finite differences reduces the degree of the polynomial by exactly one at each step. Consequently, the \omegath difference evaluates to a constant, and the next difference evaluates to exactly zero. + Taking successive finite differences reduces the degree of the polynomial by exactly one at each step. Consequently, the \omegath difference evaluates to a constant, and the next difference evaluates to exactly zero.

      Lemma: A D_0 vector of finite extent \omega generates a polynomial function of degree \omega

      @@ -2396,7 +2210,7 @@

      - Continuing to \omega = 3, the polynomial is f(t) = a_0 + a_1 t + a_2 t^2 + a_3 t^3. Evaluating the third difference D_{0,3} isolates the highest order term, yielding D_{0,3} = 6a_3. This allows immediate recovery of the highest constant: a_3 = D_{0,3} / 6. + Continuing to \omega = 3, the polynomial is f(t) = a_0 + a_1 t + a_2 t^2 + a_3 t^3. Evaluating the third difference D_{0,3} isolates the highest order term, yielding D_{0,3} = 6a_3. This allows immediate recovery of the highest constant: a_3 = D_{0,3} / 6.

      @@ -2445,13 +2259,13 @@

      A pattern emerges. Because each successive forward difference operator annihilates the lowest power of t, the resulting algebraic system is upper triangular. For any extent \omega, the \omegath difference equation reduces to D_{0,\omega} = \omega! a_\omega. This structural guarantee permits a person to reliably recover a_\omega = D_{0,\omega} / \omega!. Because an initial tape of extent \omega dictates that D_{0,\omega} is nonzero, a_\omega is guaranteed to be nonzero. All subsequent lower order constants are then systematically resolved through cascading back substitution.

      - +

      To observe the formal mechanics of this progression, a person can alternatively array these relationships into a matrix equation mapping the polynomial constants, a_i, to the initial tape differences, D_{0,n}. The coefficients of this transformation are defined by the Stirling numbers of the second kind, denoted S(i,n):

      - \begin{bmatrix} D_{0,0} \\ D_{0,1} \\ D_{0,2} \\ \vdots \\ D_{0,\omega} \end{bmatrix} = + \begin{bmatrix} D_{0,0} \\ D_{0,1} \\ D_{0,2} \\ \vdots \\ D_{0,\omega} \end{bmatrix} = \begin{bmatrix} 0! S(0,0) & 0! S(1,0) & 0! S(2,0) & \cdots & 0! S(\omega,0) \\ 0 & 1! S(1,1) & 1! S(2,1) & \cdots & 1! S(\omega,1) \\ @@ -2463,7 +2277,7 @@

      - For any extent \omega, the final row of this strictly upper triangular matrix again simplifies to D_{0,\omega} = \omega! a_\omega. + For any extent \omega, the final row of this strictly upper triangular matrix again simplifies to D_{0,\omega} = \omega! a_\omega.

      @@ -2587,7 +2401,7 @@

      Evaluating this form in the first order at the point t=5 returns a (divide 0 0). It is a strange thing, because when we plot h(t) values, against t there is an obvious correct value on the curve at t=5. There is no special feature that would make it questionable.

      - +

      Suppose we move to a second order evaluation, and for places the computation does not work, we return the machine that isn't evaluating. That is similar to what we did to get (divide 0 0), but the zeros in that expression came from a prior step first order evaluation. Let us instead give the quotient composer two machines to compose, and have it return a value when reduction to the first order is possible, and return the full problem as posed to it when it can not be reduced.

      @@ -2685,7 +2499,7 @@ Figure with x variable. - +

      As Newton pointed out, we can know the differences on the D_0 row of the table from the quotient function:

      @@ -2874,13 +2688,13 @@ TTU.step() goto increment       - +

      Here TTU is the tape transport unit. It has the number to be incremented mounted on it. This number is either zero, which would mean the leftmost cell is empty, or it is of the same form as a result from a Natural Number extension machine. A TTU.read places a copy of the symbol instance found in the cell under the head into the read buffer automatically when the machine enters a new state on the programmed controller, so it is not counted as a step. In contrast, the other actions are associated with the state of the programmed controller, so when the machine arrives at a write, step, or halt node, it means that the programmed state controller has taken a step. Sequential instructions mean unconditional next state choices, whereas an if signals a conditional next state choice. The if condition is a logical proposition based on the read symbol.

      The loop form here is worth taking note of, as it will come up again. The controller executes a first action, that of a read, followed by a middle break test, and then the recursive form actions.

      - Each row shows an input tape, and actions taken to write the result tape. For any given row, the result tape is the same as the input tape on the next row down. The table lists 7 increments, which is sufficient to reach the maximum count that can be held by a 3 bit counter. + Each row shows an input tape, and actions taken to write the result tape. For any given row, the result tape is the same as the input tape on the next row down. The table lists 7 increments, which is sufficient to reach the maximum count that can be held by a 3 bit counter.

      @@ -3060,7 +2874,7 @@

      The left neighbor cell to the leftmost cell of a given area is considered to be the left neighbor cell to the area. Similarly, the right neighbor cell to the rightmost cell of a given area is considered to be the right neighbor cell to the area. If the given area is located at the left end of the tape, then it has no left neighbor cell. If the given area is open on the right, then it has no right neighbor cell.

      -

      A tape partition is a set of areas that completely span a tape. For any partition of a single ended Turing Machine tape, at least one of the areas will necessarily be infinite. +

      A tape partition is a set of areas that completely span a tape. For any partition of a single ended Turing Machine tape, at least one of the areas will necessarily be infinite.

      Head partition

      @@ -3125,7 +2939,7 @@

      - It follows that if knowledge of the end of the active area is needed, this information must be encoded as a message. For example, a special symbol can be reserved in the alphabet specifically to serve as the end of active area marker. Each time a machine steps beyond the current end of active area marker and does a write, it writes the marker in the right neighbor cell, and goes back and erases the old mark. This method is related to communications theory and the science of signaling. Here, the active area marker is an out of band control signal. + It follows that if knowledge of the end of the active area is needed, this information must be encoded as a message. For example, a special symbol can be reserved in the alphabet specifically to serve as the end of active area marker. Each time a machine steps beyond the current end of active area marker and does a write, it writes the marker in the right neighbor cell, and goes back and erases the old mark. This method is related to communications theory and the science of signaling. Here, the active area marker is an out of band control signal.

      @@ -3133,7 +2947,7 @@

      - By definition, a computation must finish in a finite number of steps. It follows that the active area when a Turing Machine halts a computation will always be finite. Consequently, if a Turing Machine initially starts working with a tape that was computed by another Turing Machine, the length of the input will be finite. Still, that input will be in the active area, so the receiving Turing Machine will need to read control data left on the tape under a common communication protocol to be able to find the bounds of the input area. + By definition, a computation must finish in a finite number of steps. It follows that the active area when a Turing Machine halts a computation will always be finite. Consequently, if a Turing Machine initially starts working with a tape that was computed by another Turing Machine, the length of the input will be finite. Still, that input will be in the active area, so the receiving Turing Machine will need to read control data left on the tape under a common communication protocol to be able to find the bounds of the input area.

      @@ -3141,7 +2955,7 @@

      In band and out of band control

      - +

      Because of the impossibility of recognizing certain tape features, when a tape is written by one Turing Machine, then used by another, there must be some sort of system for messaging control. There are two approaches for mixing data and control together: one is in band signaling, while the other is out of band signaling.

      @@ -3156,7 +2970,7 @@

      Virtual cells

      -

      A given finite area that is not sitting on the end of the tape will have a left neighbor area and right neighbor area that are not in the area. If the given area is sitting on the end of the tape there will be no left neighbor area. If the area is open on the right, there will be no right neighbor area.

      +

      A given finite area that is not sitting on the end of the tape will have a left neighbor area and right neighbor area that are not in the area. If the given area is sitting on the end of the tape there will be no left neighbor area. If the area is open on the right, there will be no right neighbor area.

      Now imagine we define a Turing Machine such that when it steps right, it steps to the right neighbor area, and when it steps left, if there is a left area, it steps to that, otherwise it returns a left-of-leftmost symbol. The read instruction reads all of the cells in the area, and similarly the write instruction writes them all. Then for this machine the areas are virtual tape cells.

      @@ -3171,7 +2985,7 @@

      Various portions of this text have mentioned calling a Turing Machine as a subroutine. This is described as unmounting the tape from the calling machine, mounting it on the subroutine machine, running the subroutine machine until it halts, then unmounting the tape from the subroutine machine, and mounting it back on the calling machine. However, this would be a manual process. To automate the process, we use a Universal Turing Machine. It has the definition for the calling machine and the subroutine machine on its tape. We can add an additional tape to the machine to hold the stack. Then a subroutine call happens much as it does in conventional software.

      -

      A gasket machine is actually a set of subroutines with one corresponding to each of the tape transport commands. +

      A gasket machine is actually a set of subroutines with one corresponding to each of the tape transport commands.

      @@ -3298,14 +3112,14 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos \aleph_{0} - \aleph_{-1} = 1 - +

      Neither machine can be run. However we can compose the two machines, then simplify the composition. When we do so, the ever larger Natural Number machines annihilate each other, and the increment machine remains. The increment machine can be run, so we end up with an output value.

      Size

      - +

      Consider the case of a partitioned tape. Then consider that we write a gasket, such that we have a higher level Turing Machine that considers each of the areas of the partition as a cell. So then, initially the Turing machine starts with its head on the leftmost area, stepping right steps to the right neighbor area etc. In this manner we abstract the concept of a cell to areas. A length then becomes a count of areas; however the size remains a count of the cells. Something similar is done in the C language, where the length of an array is a count of the elements in the array, but the size of the array is a count of bytes. A byte being an addressable unit in physical memory, and thus the underlying cell that everything is built up from.

      Multiple machines and sharing tapes @@ -3360,7 +3174,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      - When the base machine tape cells behind an abstract area are physically contiguous, we say that the abstract area is compact. In the odd even tape partition example, the abstract areas lack compactness. + When the base machine tape cells behind an abstract area are physically contiguous, we say that the abstract area is compact. In the odd even tape partition example, the abstract areas lack compactness.

      Zero length is a second order concept @@ -3376,7 +3190,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      However we have a couple of problems, if there is no cell on the tape that has the special property. The area marking machine will step right without halting while looking for the marker. As a second problem, if the all the cells to right of the leftmost area cell, the area marker machine will never halt.

      - +

      Now suppose we employ a second order analysis.

      @@ -3431,19 +3245,19 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      Need for the concept of cell

      Let us ask a question, what is it that an address is actually locating? Let us consider this question in the light of an example. Suppose we have the tape sequence of:

      - + - a, b , c, ε, ε, ε … + a, b , c, ε, ε, ε …

      Now consider that we have an address of '2'. If we read tape address 2 we get back the letter 'c'. So the address is locating the 'c'. Now suppose we write at address 2. Say we write 'γ'. Now our sequence is:

      - + a, b , γ, ε, ε, ε …

      Now we write 'Г', resulting in the sequence:

      - + a, b , Г, ε, ε, ε … @@ -3451,7 +3265,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      It would appear that the answer to our question is that address 2 is locating different things at different times. First it was, c, then γ, then Г. Yet the address did not change. It feels a little unsatisfactory to suggest that our concept of location depends on the value addressed. Also, notice, that when we made the Natural Number Turing Machine, that the values on the tape that was placed into correspondence with the Natural Numbers were never mentioned. Yet, we can't seem to answer the question of 'what is being addressed' without giving a value.

      Addresses speak to the structure of the tape rather than the values held on the tape. So as to facilitate this interpretation, we note that a sequence consists of a sequence of cells holding elements, rather than being simply a sequence of elements. Given the concept of a cell we can say that an address always locates the same cell, though the contents of that cell can change.

      - +

      This operates similarly to a small extension to the already existing concept of a variable in mathematics. In mathematics we allow that a variable can take on different values, though its name never changes. Now we are going to say that a cell can take on different values, though its address never changes. Furthermore, as the cell is part of the sequence, we are going to say the cell itself has a left neighbor or right neighbor, excluding the value in the cell.

      Address of an area

      @@ -3524,13 +3338,13 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos f | FF - + t | FT - + x | TF - + z | FF @@ -3755,11 +3569,11 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      - A Turing Machine program faces a situation analogous to physical constraints. Given the operands are found on the tape, and the carry-in can affect the msb of the sum, the head will have to move ever more cells rightward to convey that lsb information up to the msb. Based solely on the propagation time of that information, addition is found to be a linear time algorithm. This propagation remains computation class limiting even if the Turing Machine is given an unbounded number of independent heads. + A Turing Machine program faces a situation analogous to physical constraints. Given the operands are found on the tape, and the carry-in can affect the msb of the sum, the head will have to move ever more cells rightward to convey that lsb information up to the msb. Based solely on the propagation time of that information, addition is found to be a linear time algorithm. This propagation remains computation class limiting even if the Turing Machine is given an unbounded number of independent heads.

      - There appears to be alignment among physical limitations, resource limited computing, and steps spent by Turing Machines while they carry information across a linear tape. This alignment indicates that a reasonable realization will be computation theoretic inconsequential. + There appears to be alignment among physical limitations, resource limited computing, and steps spent by Turing Machines while they carry information across a linear tape. This alignment indicates that a reasonable realization will be computation theoretic inconsequential.

      @@ -3826,7 +3640,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      Branch prediction saves the time required to do a full fetch, but fundamentally it does not change the data flow graph of the program. The same decisions are made.

      - +

      Suppose that an organization keeps the operands for a function in a content-addressable memory. When the operands are recognized, it then immediately returns the looked-up value. This approach, called memoization, bypasses the internal looping of the function. Hence, this does participate in the decision making of a program, and could potentially change the computation theoretic complexity of programs with certain properties where the same operands occur in patterns and lead to an expensive computation. Memoization is typically designed into computer languages, rather than being built into the organization of a computer. Chances are, at the computer organization level or lower, it is more efficient to simply execute the presented instructions.

      @@ -3883,8 +3697,8 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos > git clone http://www.github.com/Thomas-Walker-Lynch/tm Cloning into 'tm'... - remote:Counting objects: 3052, done. - remote:Total 3052(delta 0),reused 0(delta 0),pack-reused 3052 + remote:Counting objects: 3052, done. + remote:Total 3052(delta 0),reused 0(delta 0),pack-reused 3052 Receiving objects: 100% (3052/3052),2.41 MiB|1.52 MiB/s,done. Resolving deltas: 100% (2366/2366),done. > cd tm @@ -3939,20 +3753,20 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      Synonyms

      - (defmacro defsynonym (old-name new-name) - "Define OLD-NAME to be equivalent to NEW-NAME." - `(defmacro ,new-name (&rest args) `(,',old-name ,@args)) - ) - (defconstant ∅ nil) - (defsynonym /= ≠) - (defsynonym <= ≤) - (defsynonym >= ≥) - (defsynonym not ¬) - (defsynonym and ∧) - (defsynonym or ∨) - (defsynonym string/= string≠) - (defsynonym string<= string≤) - (defsynonym string>= string≥) + (defmacro defsynonym (old-name new-name) + "Define OLD-NAME to be equivalent to NEW-NAME." + `(defmacro ,new-name (&rest args) `(,',old-name ,@args)) + ) + (defconstant ∅ nil) + (defsynonym /= ≠) + (defsynonym <= ≤) + (defsynonym >= ≥) + (defsynonym not ¬) + (defsynonym and ∧) + (defsynonym or ∨) + (defsynonym string/= string≠) + (defsynonym string<= string≤) + (defsynonym string>= string≥) (defsynonym lambda λ) @@ -3964,7 +3778,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos * (q a b c) - (A B C) + (A B C)

      {…} - unevaluated list

      @@ -4165,7 +3979,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      The latency table above speaks to the physical reality that constrains all programs, entirely independent of their theoretical complexity class. This illustrates why computer architects spend almost their entire effort designing machines that execute as many instructions per cycle as possible, operating within a memory subsystem mathematically optimized to keep data in the lowest latency tiers. As a demonstration of this industry focus, there is not a single chapter dedicated to computation theory in Hennessy and Patterson's definitive textbook on the subject John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. (Cambridge: Morgan Kaufmann, 2017)..

      - +
      @@ -4216,7 +4030,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      - The competing standard, initially backed by Intel and soon adopted as the IEEE standard, demanded accuracy to the last bit for each operation, alongside synchronized interrupts. This predictable structure permitted a program to overflow, promote the value, and seamlessly continue an operation. It also specified the use of error tags that participate in a higher order error algebra. This standard ultimately prevailed because its precision guarantees and deterministic predictability provided the necessary foundation for the formal analysis of programs. + The competing standard, initially backed by Intel and soon adopted as the IEEE standard, demanded accuracy to the last bit for each operation, alongside synchronized interrupts. This predictable structure permitted a program to overflow, promote the value, and seamlessly continue an operation. It also specified the use of error tags that participate in a higher order error algebra. This standard ultimately prevailed because its precision guarantees and deterministic predictability provided the necessary foundation for the formal analysis of programs.

      @@ -4336,7 +4150,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

      Thus, while a Turing Machine extending the function only requires a simple accumulator, a machine tasked with multiplying two initial tapes must perform a combinatorial cross multiplication to generate the expanded tape before the extension sequence can begin. -

      +

      Division and the Reciprocal Difference Vector

      diff --git a/document/book/TTCA_machine.svg b/document/book/TTCA_machine.svg index 1cfc912..0e0b38f 100644 --- a/document/book/TTCA_machine.svg +++ b/document/book/TTCA_machine.svg @@ -22,15 +22,15 @@ inkscape:pagecheckerboard="0" inkscape:deskcolor="#d1d1d1" showgrid="true" - inkscape:zoom="1.5540715" - inkscape:cx="467.80344" - inkscape:cy="447.21236" - inkscape:window-width="1920" - inkscape:window-height="1131" - inkscape:window-x="0" - inkscape:window-y="32" - inkscape:window-maximized="1" - inkscape:current-layer="svg311">Next StateNext StateTable (δ)TabledecoderGate Decoder==rightmostTTU [n]TTU [1]TTU [0]datadataUNIT 0TAPE...q one hotq one hotstatusstatuscommandControlControlmotorAction TableAction Table (λ)Table dHaltHaltSwitchSwitchBankBank + id="rect39862" + width="54.063389" + height="37.38728" + x="559.95764" + y="219.98454" />clkreset