From: Thomas Walker Lynch Date: Tue, 7 Jul 2026 02:09:18 +0000 (+0000) Subject: . X-Git-Url: https://git.reasoningtechnology.com/%28%5B%5E?a=commitdiff_plain;h=2f40ed31adcaa7a45d4b1218de6ccc99cd36eb8e;p=TM-2026 . --- diff --git a/document/TM-2026.html b/document/TM-2026.html index d7255dd..be015be 100644 --- a/document/TM-2026.html +++ b/document/TM-2026.html @@ -1062,7 +1062,7 @@ At a higher level, that virtual memory system level, the memory architecture begins to look more like that of a Turing Machine. The translation lookaside buffer provides stateful location context, and the neighbor relationship between pages might be taken into account for performance reasons. However, once a program starts performing at virtual memory page fetch times instead of local system memory access times, we say that it is page thrashing and know it will become too slow to wait on, no matter its computation complexity class. Aliasing can happen in the virtual memory system, which, when it happens, can cause programs to become very slow.

-Area and partitioning + Area and partitioning

We call a subset of contiguous cells from a tape an area. An area with a single cell is called a singleton, one with two cells is called a pair. An area has a leftmost cell and a rightmost cell. For a singleton area, those will be the same cell.