From: Thomas Walker Lynch Date: Sat, 25 Jul 2026 16:29:55 +0000 (+0000) Subject: better block diagram, still some machine issues X-Git-Url: https://git.reasoningtechnology.com/%27%20%20%20window.RT.dirpr_library%20%20%20%27/Hindu-Arabic%20number%20fig%203.png?a=commitdiff_plain;h=ae1f83a655933d3390125e0476965dadd06678df;p=TM-2026 better block diagram, still some machine issues --- diff --git a/document/book/TM-2026.html b/document/book/TM-2026.html index 520f5cf..538842a 100644 --- a/document/book/TM-2026.html +++ b/document/book/TM-2026.html @@ -722,11 +722,11 @@ -

q: is the current state of the machine.

+

q: is the current state of the machine.

-

d: is the data register.

+

d: is the data register.

-

g: is the gate register.

+

g: is the gate register.

The TTCA Machine programmable part

@@ -757,7 +757,7 @@
δ_1 = \{ \langle q_0, r{·}σ, q_1 \rangle, \dots \}
-

where q_0 is matched to the current state of the machine. r{·}σ is a symbol in register r, where r is either d or g. q_1 is the next state. When q_0 matches the current state, q_1 becomes the next state. Both q_0 and q_1 come from the total set Q. σ comes from the total set Σ.

+

where q_0 is matched to the current state of the machine. r{·}σ is a symbol in register r, where r is either d or g. q_1 is the next state. When q_0 matches the current state, q_1 becomes the next state. Both q_0 and q_1 come from the total set Q. σ comes from the total set Σ.

The default transition table. A set of state transition pairs; each pair is of the form:

@@ -811,31 +811,33 @@

To execute the programmed TTCA Machine, a person must maintain the current machine variables MV and evaluate the programmed logic in an repeating two-phase cycle, until a halting state is reached. Because this is a Moore-style architecture, the execution of an action is isolated from the evaluation of the next state transition.

-

Initialization

+

Initialization stage

Before the first cycle begins, a tape is selected and mounted. The read/write head is positioned over the leftmost tape cell. The machine variables are initialized as follows:

+ +

Programmed control stage

-

Phase 1: The action

+

Phase 1: The action

During the action phase, the executor looks up the operation mapped to the current state.

    -
  1. Locate the current state q within the programmed actions set λP.
    2. +
  2. Locate the current state q within the programmed actions set λP.
  3. Perform the associated action a \in AF.
-

Phase 2: The state transition

+

Phase 2: The state transition

Following the completion of the action, the executor evaluates the next state by cascading through the ordered sequence of transition rules δ = [δF_0 | δ_1 | δ_2 | δ_3]. The evaluation follows this hierarchy, stopping and branching at the first valid match:

    -
  1. Evaluate δF_0: Inspect the gate register g. If it holds the ΣF{·}\mathtt{unspecified} symbol, the next state becomes QF{·}\mathtt{unspecified\_decision}. This halts standard programmed execution.
    2. -
  2. Evaluate δ_1: Search the programmed conditional rules for a triple that matches the current state q and the exact symbol currently held in the gate register g. If a match is found, the next state updates to the specified q_1.
    3. -
  3. Evaluate δ_2: If no conditional rule matches, search the programmed default rules for a pair matching the current state q. If a match is found, the next state updates to the specified q_1.
    4. +
  4. Evaluate δF_0: Inspect the gate register g. If it holds the ΣF{·}\mathtt{unspecified} symbol, the next state becomes QF{·}\mathtt{unspecified\_decision}. This halts standard programmed execution.
    5. +
  5. Evaluate δ_1: Search the programmed conditional rules for a triple that matches the current state q and the exact symbol currently held in the gate register g. If a match is found, the next state updates to the specified q_1.
    6. +
  6. Evaluate δ_2: If no conditional rule matches, search the programmed default rules for a pair matching the current state q. If a match is found, the next state updates to the specified q_1.
  7. Evaluate δ_3: If all prior evaluations fail to yield a match, unconditionally update the next state to the global fallback transition specified by δ_3.
-

Continuation

+

Halting stage

If the machine reaches a point where there is no next state, or the head has walked off of the tape, the machine hangs. If, after the state transition phase completes, the current state is a member of H, the machine halts. Otherwise the cycle repeats.

@@ -1228,7 +1230,7 @@
Figure 1 A Turing Machine
-

The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few modifications. The architecture has no 'unspecified' symbol. Rather, an actual value is transacted. Now that data and control have been separated, the controller is practical to implement, and even more so because it was defined in terms of tables that can be built in hardware. As the status command returns the cell type, it will in its current form be able to return 'rightmost', so that the right end of the tape can be detected. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. This could be signaled either by a panel light that illuminates upon the machine finding a rightmost status, or by the program printing a message on the console teletype. As this is a constant time operation, it is computation theoretic inconsequential.

+

The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few modifications. The architecture has no 'unspecified' symbol. Rather, an actual value is transacted. Now that data and control have been separated, the controller is practical to implement, and even more so because it was defined in terms of tables that can be built in hardware. As the status command returns the cell type, it will in its current form be able to return 'rightmost', so the right end of the tape can be detected. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. This could be signaled when the user attempts to step right of rightmost, either by a panel light that illuminates upon the machine finding a rightmost status, or by the program printing a message on the console teletype. As this is a constant time operation, it is computation theoretic inconsequential.

Because a Turing Machine can only reach another cell further out on the tape by stepping to it, space complexity and time complexity are related. A program that runs for ten steps can consume at most ten cells of tape. However, if that program merely bounces between two cells, it will require less space, precisely two cells. As another example, a program that counts the number of characters on its input tape using Arabic notation will execute in asymptotically linear time, as demonstrated later in the section analyzing the increment operation. Its working footprint, however, will be logarithmic in space complexity, because that is how fast an Arabic representation grows with a count.

@@ -1239,15 +1241,15 @@

This book provides the transformational steps needed to go from the Turing Machine to real machines, and one objective is to recover some correspondence between the machine steps of the model and the wall-clock time the machine takes to run. Given this, the system operator changing tapes creates a step that is disproportionately longer than the other steps, a factor that requires architectural mediation, but will always remain. For example, this structural penalty resurfaces in the form of cache misses causing a machine to reach into system memory, or worse, page faults, requiring a machine to go back to disk.

-

As a possible practical solution, note that if the program does not exhaust the current tape, the operator will never be called. How much tape is required to ensure this? An analyst could choose worst-case operands and measure the footprint when the program runs. At first, this appears to be the familiar 'my number is bigger than your number, I'll tell you mine after you tell me yours' game, which can be viewed as the definition for the countable infinity. However, there is a loophole. Running the system once with the worst-case operands to establish time and space ceilings guarantees the program can be allocated sufficient resources later for other operands. This is a practical approach, provided the program is a workhorse utility rather than an algorithm searching for a solution to an unsolved problem that only needs to run once.

+

As a possible practical solution, note that if the program does not exhaust the current tape, the operator will never be called. How much tape is required to ensure this? An analyst could choose worst-case operands and measure the footprint when the program runs. At first, this appears to be the familiar 'my number is bigger than your number, I'll tell you mine after you tell me yours' game, which can be viewed as the definition for the countable infinity. However, there is a loophole. Running the system once with the worst-case operands to establish time and space ceilings guarantees the program can be allocated sufficient resources later for other operands. This is a practical approach, provided the program is a workhorse utility rather than an algorithm searching for a solution to an unsolved problem, so it only needs to run once.

-

Another practical solution, one that also applies to the first run of the program, is to analyze the logic to compute the time per step and extrapolate the total execution time. This is not universally possible; for some programs, tracing a path through the execution logic is as computationally complex as running the program itself, taking us back to the analysis in the prior paragraph. However, this boundary does not apply to all systems. Consider the previously mentioned examples of the ten step machine, the machine bouncing between two cells, and the Arabic counting machine.

+

Another practical solution, one that also applies to the first run of the program, is to analyze the logic to compute the time per step and extrapolate the total execution time. This is not universally possible; for some programs, tracing a path through the execution logic is as computationally complex as running the program itself, taking us back to the analysis in the prior paragraph. However, this phenomena does not apply to all programs. Consider the previously mentioned examples of the ten step machine, the machine bouncing between two cells, and the Arabic counting machine.

-

Suppose a controller is not analyzed to determine its computation theoretic complexity, or even tested against worst-case inputs, but is instead run with random or everyday input to gather performance measurements. This process is called profiling. After many runs, a programmer might surmise the behavioral limits of the program. However, many programs are neither linear systems nor smooth functions. With a different set of inputs than those used for profiling, perhaps even values adjacent to prior inputs, the program behavior can shift drastically. Consider the Pentium divider. It did not matter how many millions of times the result was accurate; the fact remains that customers later found an input that yielded wildly inaccurate results. Only by elevating the analysis to the structural logic of the code can such an eventuality from an erroneous algorithm be categorically ruled out. This is why the K5 transcendental function development project included a proof writing phase; see Thomas Walker Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, "The K5 Transcendental Functions," Proceedings of the 12th IEEE Symposium on Computer Arithmetic, 1995. DOI: 10.1109/ARITH.1995.465368.

+

Suppose a controller is not analyzed to determine its computation theoretic complexity, or even tested against worst-case inputs, but is instead run with random or everyday input to gather performance measurements. This process is called profiling. After many runs, a programmer might surmise the behavioral limits of the program. However, many programs are neither linear systems nor smooth functions. With a different set of inputs than those used for profiling, perhaps even values adjacent to prior inputs, the program behavior can shift drastically. Consider the Pentium divider. It did not matter how many millions of times the result was accurate; the fact remains that customers later found an input that yielded wildly inaccurate results. Only by elevating the analysis to the structural logic of the code can such an eventuality from an erroneous program be categorically ruled out. This is why the K5 transcendental function development project included a proof writing phase; see Thomas Walker Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, "The K5 Transcendental Functions," Proceedings of the 12th IEEE Symposium on Computer Arithmetic, 1995. DOI: 10.1109/ARITH.1995.465368.

-

Head unit, HU

+

Head unit, HU

-

An HU contains a head and a local controller. The local controller supports these commands:

+

An HU contains a head and a local controller. The local controller supports these commands:

  1. read → σ
    2. @@ -1255,9 +1257,9 @@
  2. status → γ
-

One or more head units are plugged into the TTU, which is described in the next section. Commands are only sent to the head unit when a tape is mounted on the TTU, and they are sent by the TTU. The machine at large does not have an interface to the HU.

+

One or more head units are plugged into the TTU, which is described in the next section. The TTU only sends commands when a tape is mounted.

-

The status command returns the name of the cell type of the cell the head is on. The head controller communicates with other components of the machine to ascertain the status, which is one of:

+

On this model of machine, the HU status is identical to the cell type. The cell type does not come from the tape, so the HU must work in conjunction with the TTU to derive its value. In review the cell types are:

  1. leftmost
    2. @@ -1266,21 +1268,23 @@
  2. island
-

A status of rightmost or island would never be returned for a computation theoretic Turing Machine tape, but it can be for an area of a tape, and such an area can be an abstract virtual tape, as is described in the later section on Area.

+

A status of rightmost or island would never be returned for a computation theoretic Turing Machine tape. This is where having a finite extendable tape can differ from that of a single ended theoretical object.

+ +

Each HU has a data buffer that can be read or written, and a status buffer that can be read.

-

Tape transport unit, TTU

+

Tape transport unit, TTU

-

The TTU is the component where tapes are mounted and unmounted, and where read/write heads are installed. When multiple heads are plugged in, the controller passes control among them so it appears that heads never collide. The TTU controller has these components: +

The TTU is the component where tapes are mounted and unmounted, and where read/write head units are installed. When multiple HUs are plugged in, the controller passes control among them so it appears that heads never collide. The TTU controller has these components:

    -
  1. one or more read/write heads
    2. -
  2. a single symbol FIFO read data buffer, written by the TTU, read by the executor
    3. -
  3. a single symbol FIFO status buffer, written by the TTU, read by the executor
    4. -
  4. a single symbol FIFO command buffer, written by the programmed controller, acted upon immediately by the TTU
    5. +
  5. one or more HUs
    6. +
  6. a data buffer holding a single symbol
    7. +
  7. a status buffer
    8. +
  8. a single symbol FIFO command buffer, written by the programmed controller, acted upon immediately by the TTU
-

The TTU interfaces with the executor, which in turn gates the flow of data through the machine. The executor controls the clock and reset lines, and through this supervises the customer programmed control unit, the CPCU. This two-layer control system is single-threaded and issues the following commands to each selected TTU:

+

The TTU interfaces with the executor, which in turn gates the flow of data through the machine. The executor controls the clock and reset lines, and through this supervises the customer programmed control unit, the CPCU. This two-layer control system is single-threaded and issues the following commands to each selected TTU:

  1. read head → σ
    2. @@ -1290,17 +1294,17 @@
  2. right
-

For the first three commands, the head argument multiplexes the command to the specified head. If the TTU has one head, the head argument is optional. The last two commands cause the tape to be moved such that, relatively, the head moves left or right by one cell.

+

For the first three commands, the head argument multiplexes the command to the specified head. If the TTU has one head, the head argument is optional. The last two commands cause the tape to be moved such that, relatively, the head moves left or right by one cell.

-

The customer programmed control unit, CPCU

+

The customer programmed control unit, CPCU

The controller is programmed via patch panels. The panels would look something like what is shown in the following ASCII art blocks. Note that ● indicates an illuminated indicator light, whereas ○ is not illuminated. [/] represents an open toggle switch, while [—] is a closed one. {*} is a pushed button, while { } is a button that is not pushed. ( ) represents a hole for a banana plug. Each patch cord has a banana plug on each end. Plugging a patch cord between separate panels will void the warranty.

                           [ CONTROL PANEL ]
                 +-----------------------------------+
-                | POWER [—]  ●  RESET { }           |
+                | POWER [—] ●  ERROR ○    RESET { } |
                 +-----------------------------------+
                 +-----------------------------------+
                 | RUN/STEP [/]  ○  STEP { }         |
@@ -1359,7 +1363,7 @@
                    +-----------------------------------+
-

The top section has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Immediately to the right of the two toggles are indicator lights. To the right of the indicator lights are two push buttons. One is for reset, which sends the machine back to state S_0, and the other is for stepping the machine when it is in single-step mode.

+

The top section has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Immediately to the right of the two toggles are indicator lights. To the right of the indicator lights are two push buttons. One is for reset, which sends the machine back to state S_0, and the other is for stepping the machine when it is in single-step mode. This panel also has an error indicator light which will illuminate if no next state is specified for a state transition, and thus the machine is hung.

The second section is the state transition panel. At the top of this panel are the state indicator lights and a row of halting toggles; if flipped closed, the corresponding state becomes a halting state. Below this is the transition condition matrix, consisting of holes that fit the banana plug ends of a patch cord. Each column corresponds to a current state, and each row corresponds to a gate symbol.

@@ -1369,8 +1373,7 @@

To program the controller, the programmer connects the patch cords. For example, routing a patch cord from the (S_2, g_2) intersection to S_3 physically realizes a state transition arc for the controller. If the active gating value has no patch cord plugged in, the machine instead uses the state default transition. For a state default transition, a patch cord is plugged into the column for the current state on the default transition panel and routed to the desired next state. Finally, if no patch cord is plugged in that would otherwise define the next state, the global default patch cord is followed.

-

Below the transition panel are the action selection and symbol selection panels. To enforce the rule that each state executes exactly one action, each state column on the action panel features a single source hole at the top. The programmer routes a patch cord from this source hole down to the desired action row. If the selected action requires a symbol argument, such as write_σ, a similar routing is performed on the bottom symbol selection panel. Note that this describes the control panel for a single-head, single-TTU machine. Additional patch options would be required to add a TTU device specifier and a head specifier within each TTU.

- +

Below the transition panel are the action selection and symbol selection panels. To enforce the rule that each state executes exactly one action, each state column on the action panel features a single source hole at the top. The programmer routes a patch cord from this source hole down to the desired action row. If the selected action requires a symbol argument, such as write_σ, a similar routing is performed on the bottom symbol selection panel. Note that this describes the control panel for a single-head, single-TTU machine. Additional patch options would be required to add a TTU device specifier and a head specifier within each TTU.

The machine block diagram

@@ -1381,84 +1384,78 @@

Components

    +
  1. Control Panel +
      +
    1. Executor interface: Power Switch, Single Step Switch, Reset Button, Single Step Button
      2. +
    2. CPCU interface: Patch cord matrices
      3. +
    +
  2. Executor
      -
    1. Control Panel -
        -
      1. Power Switch
        2. -
      2. Single Step Switch
        3. -
      3. Reset Button
        4. -
      4. Single Step Button
        5. -
      -
      2. -
    2. halt state switch bank
      3. -
    3. clock and distribution lines (clk)
      4. -
    4. reset distribution lines
      5. +
    5. Halt state switch bank
      6. +
    6. Clock and phase distribution lines (clk)
      7. +
    7. Reset distribution lines
    3. -
  3. g register
    4. -
  4. status bus
    5. -
  5. Gate Decoder
    6. -
  6. d register
    7. -
  7. data bus
    8. -
  8. CPCU +
  9. CPCU (Customer Programmed Control Unit)
      -
    1. one-hot q register
      2. -
    2. next state table
      3. -
    3. action table
      4. +
    4. One-hot q register
      5. +
    5. Next-state table
      6. +
    6. Action Table
    10. +
  10. g register
    11. +
  11. Status bus
    12. +
  12. Gate Decoder
    13. +
  13. d register
    14. +
  14. Data bus
-

This is a top-level block diagram, not a schematic. It is of sufficient detail to express the organization of the machine and to guide the implementation. Not shown are the clock lines going to all clocked registers, and the reset line going to all registers. Missing also are the details of the executor control, and details of the TTU control.

+

This section describes the TTCA machine organization. The diagram above shows the major components and their channels of communications. This instructs designers who will later draft schematics that will specify all of the connections.

-

The executor provides the ultimate control of the machine, telling registers when to sample or latch, enabling bus drivers, and distributing the clock and reset signals.

+

As described in the computation theoretic section that is being used as the architectural template, "Computation theoretic TTCA Machine executor", the executor guides the machine through initialization, programmed control, and halting stages of execution. When in the programmed control stage, the CPCU most of the active control comes from the the CPCU. The Executor contains the power, reset, and clock logic. It has two modes of execution, the run mode in which the clock runs free. Secondly, the single step mode, in which clock pulses are sent with the push of a button.

-

There are two registers in the register file. The d register holds data values that are being carried. The d register has no path to the customer programmed controller. The g register holds the status value used for gating the controller.

+

The CPCU has the current state register, q, the Next State Table, and the Action Table.

-

The symbols used for status and gating the programmed controller occur within an enumeration. Each is given a value that corresponds to its row index on the control panel. The value on the status bus is then latched by the g register and goes to a decoder which has one output line per symbol. Decoding the status then results in a one-hot value sent to the state transition logic for gating to the next state. Due to the enumeration, the decoder displaces the need for a bank of comparators, each comparator checking for a distinct symbol on the status bus.

+

The output of the Action Table provides primary control of the running machine. Its output determines which of the TTUs will be active, which head in the TTU is to be used. The machine has an internal data bus. The output of the Action Table also determines which TTU register will drive that bus, and which register will receive data from the bus.

-

The current state register is a one-hot encoding, with a bit per state. A wire from each bit goes to the executor where it meets the bank of halt switches, the outputs of which are all wire-ORed together to create the halt signal. Thus, for halt to be asserted, the given state must be turned on in the switch bank.

+

The register file contains two registers, g and d. The d register is for holding data read from the tape that will not participate in the next state decision process. The g register holds either data read from the tape, or the status returned from a TTU head. Status is derived from the head's position relative to the ends of the tape. With a real tape drive, an unused leader and trailer are required to prevent the tape from departing from the reels, something that can not be easily undone, so the format, or physical, markers will be on the ends of the usable portion of the tape, rather on the physical end of the tape. The g register gets its name from the fact that its value, independent of the source, is used for gating the next state transition (when the next state comes from the main Next State Table, rather from on from one of the defaults).

-

Upon reset, the current state register is set to a one-hot configuration, with the single active bit acting as the state 0 indicator. All other machine registers are cleared to zeros. Also, the power switch has a capacitor timer that holds reset for a safe amount of time while the machine comes up.

+

The symbols of the alphabet are enumerated such that each symbol corresponds to a specific row index on the control panel. The value on of the g register is decoded, resulting in a one hot encoding of the gate symbol. This one hot encoding then goes to the Next State Table in the CPCU, and illuminates one of the rows. The q register enumerates the columns. If a patch cord is plugged into that intersection point, and leads to the next state bank below, then the next state selected in the next state bank becomes the next state for the machine.

-

- If a physical machine receives power without the reset signal being held, it can land in an illegal state. This is hazardous as the machine might become permanently stuck in a configuration that ignores subsequent reset commands, it might operate unpredictably, or it might even suffer physical hardware damage. To avoid these outcomes, systems are designed to hold the reset line active while the power comes up. Asserting the reset signal, rather than recycling power, is what actually causes a machine to land in a known initial state. Consequently, we must include a reset feature. -

+

The current state register q utilizes a one-hot encoding, allocating a discrete bit per state. A control line from each bit routes to the Halt Switch Bank within the executor, where the outputs are wire-ORed together to generate the master halt signal. Consequently, a halt condition asserts if and only if the currently active state bit corresponds to an enabled toggle in the switch bank. The output of the q register also selects a row in the Action Table.

+ -

- This design assumes that when reset is released, the machine immediately starts running. This is fine for our purposes, but surely the deluxe model would have a separate 'go' button and the associated logic. -

+

Upon reset, the current state register initializes to a one-hot configuration with the bit for state S_0 asserted, while all other machine registers clear to zero. To prevent power-on initialization hazards—where unlatched logic could trap the machine in an illegal configuration, ignore subsequent reset commands, or induce physical hardware damage—the power switch incorporates a capacitor timer that maintains an active reset signal until supply voltages fully stabilize.

- The tape transport unit, TTU, handles mounting, unmounting, reading, writing, and moving the tape. In this volume we will talk about stepping the head. This should be interpreted in a relative sense, as a real TTU will move the tape rather than the head. Our machine is designed such that the customer can plug in more than one TTU. Each unit has its own read buffer, status buffer, and head. A tape can be mounted or unmounted from each unit. At the election of the operator, the tape can be unmounted from one TTU, shelved perhaps, then unshelved and mounted back on any TTU, the same one, a different one on the same machine, or a TTU on another machine. + This design assumes that releasing the reset line causes the machine to begin execution immediately. While adequate for our baseline model, a deluxe variant would integrate a dedicated 'go' button and associated transition logic.

- The constant executor should not be conflated with the Customer Programmed Control Unit (the TTCA program). The executor is not programmable by the customer. For a microcode controlled machine, the executor procedure will be found in microcode memory, and it will be executed as though a program. Each line of the procedure, when read, results in a set of bits being connected to the machine's control lines. Some of those control lines will control what the procedure does, and some will extend out into the data path and be used to configure execution units and gate data on to busses. + The tape transport unit, TTU, handles mounting, unmounting, reading, writing, and moving the tape. In this volume, we treat head motion in a relative sense, recognizing that a physical TTU moves the magnetic tape beneath a stationary head rather than displacing the head across the tape. Our architecture allows a system to incorporate multiple TTU modules, each containing its own read buffer, status buffer, and head assembly. Tapes can be dynamically mounted, unmounted, shelved, and transferred between any TTU on the same machine or across distinct systems.

- For a hardwired machine, the executor procedure will be expressed with logic gates and flip-flops (single-bit memory registers). Whether a machine is microcode controlled or hardware controlled is a question of implementation. The values on the control lines remain the same independent of those implementation decisions. + The hardwired executor must not be conflated with the Customer Programmed Control Unit. For a microcode-controlled machine, the executor's phase sequencing procedure resides in microcode memory and executes much like a stored program, independent of the customer's payload logic. Alternatively, in a hardwired implementation, the executor logic is expressed directly via discrete logic gates and flip-flops. Whether a machine relies on microcode or hardwired logic for its internal sequencing is strictly a question of implementation, leaving the underlying architectural constraints and the CPCU interface invariant.

-

Description of a read g command

+

Description of a read_g command

-

A magnetic tape head reads when the tape is moving, so ironically it is like the Emacs cursor. The read will occur when the machine steps and the data will be waiting in the data buffer for a read command. The head will wait at the other side of the cell. Unlike the theoretical tape, there is interstitial space between the cells where the head can wait for the next command, then swipe further right. In a real machine, blocks of cells will always be read, and the buffer will be much deeper.

+

A magnetic tape head reads when the tape is moving, so ironically it is like the Emacs cursor. The read will occur when the machine steps, and the data will be waiting in the data buffer for a read command. The head will wait at the other side of the cell. Unlike the theoretical tape, there is interstitial space between the cells where the head can wait for the next command, then swipe further right. In a real machine, blocks of cells will always be read, and the buffer will be much deeper.

The current state latch, q, is open on the falling edge of the clock, and then samples and holds while the clock is high. The gate register, g, is the phase inverse; it is open while the clock is high, and samples and holds while the clock is low.

-

On the rising edge of the clock, the state is latched. The current state signal ripples through the action table. As the q register is stored as a one-hot value, this happens very quickly. Rather than placing commands in the action table, the decoded values of the commands that are needed for control are programmed directly into the table. Among the decoded outputs of the action command is a control signal that enables the opening of the gate register latch.

+

On the rising edge of the clock, the state is latched. The current state signal ripples through the Action Table. As the q register is stored as a one-hot value, this happens very quickly. Rather than placing commands in the Action Table, the decoded values of the commands that are needed for control are programmed directly into the table. Among the decoded outputs of the action command is a control signal that enables the opening of the gate register latch.

-

A control signal from the decoded command coming from the action table then enables the selected TTU, and if the TTU command is already decoded, a line will select either the TTU read register (for the read_d command) or the selected status register (for the read_g command). Both values are ready to drive the bus when the control signal arrives.

+

A control signal from the decoded command coming from the Action Table then enables the selected TTU. If the TTU command is already decoded, a line will select either the TTU read register (for the read_d command) or the selected status register (for the read_g command). Both values are ready to drive the bus when the control signal arrives.

-

At this time the q latch is enabled and open, so the selected value travels through the latch to a decoder, and then to the state transition table, where it energizes a row, reaches the patch cord, and the signal travels through the patch cord and illuminates the next state bit. This is the critical path that sets the clock period, provided that the TTU controller is not slower.

+

At this time the g latch is enabled and open, so the selected value travels through the latch to a decoder, and then to the state transition table, where it energizes a row, reaches the patch cord, and the signal travels through the patch cord and illuminates the next state bit. This is completes the critical path that sets the clock period.

During that time the clock has a falling edge, so the g register latches and holds the gate value. The q register latch opens, waiting for the critical path signal to resolve. It has the remaining low period of the clock to do so, giving it one full clock cycle to resolve.

Then the clock rises, and the cycle repeats.

- The TTCA stored program

Symbol in mathematics

@@ -2020,7 +2017,7 @@

- The divide machine cannot be run to produce a value, as any value from the field assigned to it would lead to contradictions. Stated more precisely, for x \cdot y = q operations, when given an x and a q value, there is only one possible y value, and it can be recovered with q/x. However, when x is zero, and only when it is zero, q is solely determined by x independent of y, so y is ignored; it could be any value. There is no way to recover it from q/x. + The divide machine cannot be run to produce a value, as any value from the field assigned to it would lead to contradictions. Stated more precisely, for x \cdot y = q operations, when given an x and a q value, there is only one possible y value, and it can be recovered with q/x. However, when x is zero, and only when it is zero, q is solely determined by x independent of y, so y is ignored; it could be any value. There is no way to recover it from q/x.

Evaluating and Extending

@@ -2385,7 +2382,7 @@

- We cannot do function based arithmetic on these until we synchronize them. Suppose that for each call of the f machine, there will be three calls to the g machine. So we can make a new machine that is called once, each time f is called, g(t) = 3t - 15. + We cannot do function based arithmetic on these until we synchronize them. Suppose that for each call of the f machine, there will be three calls to the g machine. So we can make a new machine that is called once, each time f is called, g(t) = 3t - 15.

@@ -2484,7 +2481,7 @@

- I included the first difference along with the evaluation results in the table above. When building a first difference table an interesting thing happens at the singularity, the first difference and the function itself coincide, note calls 4 and 5. This makes sense because \Delta f(4) = f(5) - f(4), which becomes \Delta f(4) = 0 - f(4), and the same happens to g in the denominator, so the signs cancel. Note also \Delta f(5) = f(6) - f(5), which becomes \Delta f(5) = f(6) - 0. + I included the first difference along with the evaluation results in the table above. When building a first difference table an interesting thing happens at the singularity, the first difference and the function itself coincide, note calls 4 and 5. This makes sense because \Delta f(4) = f(5) - f(4), which becomes \Delta f(4) = 0 - f(4), and the same happens to g in the denominator, so the signs cancel. Note also \Delta f(5) = f(6) - f(5), which becomes \Delta f(5) = f(6) - 0.

Ostensibly it looks like we have happened upon a discrete version of L'Hôpital's rule, that we merely use the first difference quotient instead of the function quotient at the singularity. But alas, the coincidence occurs at h(4) rather than at h(5). For the second coincidence, we find h(6) as the 5th first finite difference. In neither case did we learn anything about the value of h(5). diff --git a/document/book/TTCA_machine.svg b/document/book/TTCA_machine.svg index 0e0b38f..ade5ebc 100644 --- a/document/book/TTCA_machine.svg +++ b/document/book/TTCA_machine.svg @@ -22,26 +22,26 @@ inkscape:pagecheckerboard="0" inkscape:deskcolor="#d1d1d1" showgrid="true" - inkscape:zoom="1.2036126" - inkscape:cx="468.58933" - inkscape:cy="402.53817" - inkscape:window-width="1436" - inkscape:window-height="736" - inkscape:window-x="948" - inkscape:window-y="407" - inkscape:window-maximized="0" - inkscape:current-layer="g18206">TTU 2TTU 1==rightmostTTU [n]==rightmostTTU [1]TTU [0]dataTTU 0HEADUNIT 0TAPE......q one hotstatusControlControlmotormotordHaltSwitchBankEXECUTORclkreset + id="path40566" />HU 2controlstatusdataHU 1controlstatusdataHU 0controlstatusdataHaltSwitchBankEXECUTORclkresetrun/step