From: Thomas Walker Lynch Date: Tue, 28 Jul 2026 17:20:53 +0000 (+0000) Subject: . X-Git-Url: https://git.reasoningtechnology.com/%27%20%20%20window.RT.dirpr_library%20%20%20%27/%7Bstyle.link%7D?a=commitdiff_plain;h=1c5f2f50cd7e971ba86bf56cbb49a810a266d874;p=TM-2026 . --- diff --git a/document/book/TM-2026.html b/document/book/TM-2026.html index 74a4d9b..10bf366 100644 --- a/document/book/TM-2026.html +++ b/document/book/TM-2026.html @@ -1264,14 +1264,14 @@

-The TTCA Machine design + The TTCA Machine design
Figure 1: A Turing Machine
Figure 1: A Turing Machine
-

The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few modifications. The architecture requires explicit data rather than accepting meta-symbols like 'unspecified' as presumed initial values 'by definition'. Actual values are transacted. Now that data and control have been separated, the controller is practical to implement, and even more so because it was defined in terms of tables that can be built in hardware. As the status command returns the cell type, it will in its current form be able to return 'rightmost', so the right end of the tape can be detected. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. This could be signaled when the user attempts to step right of rightmost, either by a panel light that illuminates upon the machine finding a rightmost status, or by the program printing a message on the console teletype. As this is a constant-time operation, it is computation theoretic inconsequential.

+

The prior chapter on the computation theoretic TTCA machine serves as the architectural template, with only a few modifications. The architecture requires explicit data rather than accepting meta-symbols like 'unspecified' as presumed initial values 'by definition'. Actual values are transacted. Now that data and control have been separated, the controller is practical to implement, and even more so because it was defined in terms of tables that can be built in hardware. As the read status instruction returns the cell type, it will in its current form be able to return 'rightmost', so the right end of the tape can be detected. In order to extend the tape, the machine will stop and ask the operator to mount a new reel. This could be signaled when the user attempts to step right of rightmost, either by a panel light that illuminates upon the machine finding a rightmost status, or by the program printing a message on the console teletype. As this is a constant-time operation, it is computation theoretic inconsequential.

Because a Turing Machine can only reach another cell further out on the tape by stepping to it, space complexity and time complexity are related. A program that runs for ten steps can consume at most ten cells of tape. However, if that program merely bounces between two cells, it will require less space, precisely two cells. As another example, a program that counts the number of characters on its input tape using Arabic notation will execute in asymptotically linear time, as demonstrated later in the section analyzing the increment operation. Its working footprint, however, will be logarithmic in space complexity, because that is how fast an Arabic representation grows with a count.

@@ -1289,7 +1289,7 @@

Head Unit, HU

-

An HU contains a head and a local controller. The local controller supports these commands:

+

An HU contains a head and a local controller. The local controller supports these instructions:

  1. read() → σ
    2. @@ -1297,7 +1297,7 @@
  2. status() → s
-

On this model of machine, the HU status is identical to the indicated cell's type. The cell type is not read from the tape; rather, it is derived from the head's physical relationship to the ends of the tape. Consequently, the HU works in conjunction with the TTU to derive the status. (The tape transport unit, the TTU, is discussed in the next section.) As established in the section discussing cells, cell types are:

+

On this model of machine, the HU status is identical to the indicated cell's type. The cell type is not read from the tape; rather, it is derived from the head's physical relationship to the ends of the tape. With a real tape drive, an unused leader and trailer are required to prevent the tape from departing from the reels, a condition difficult to reverse. Therefore, the format, or physical, markers will be on the ends of the usable portion of the tape, rather than on the physical end of the tape. Consequently, the HU works in conjunction with the TTU to derive the status. (The tape transport unit, the TTU, is discussed in the next section.) As established in the section discussing cells, cell types are:

  1. leftmost
    2. @@ -1310,7 +1310,7 @@

    For a realized TTU, data can only be read or written when there is relative motion between the head and the tape. Consequently, in an HU implementation, data and status registers are updated from an internal buffer that acquires data during head motion. Conversely, a write value is buffered until subsequent head motion provides the opportunity to write it to the tape.

    -

    Because values can only be read or written to a tape when the tape is in motion, it is advantageous to exaggerate the motion of step commands and to cache a small number of values. In addition, most architectures that make use of a tape drive will attempt to leverage high throughput in an effort to hide high latency by reading or writing blocks of symbols per tape access. Note, however, that the basic TTCA Machine organization lacks the core memory required for buffering blocks.

    +

    Because values can only be read or written to a tape when the tape is in motion, it is advantageous to exaggerate the motion of step instructions and to cache a small number of values. In addition, most architectures that make use of a tape drive will attempt to leverage high throughput in an effort to hide high latency by reading or writing blocks of symbols per tape access. Note, however, that the basic TTCA Machine organization lacks the core memory required for buffering blocks.

    Tape transport unit, TTU

    @@ -1321,10 +1321,10 @@
  2. one or more HUs
  3. a data buffer holding a single symbol
  4. a status buffer
    5. -
  5. a command buffer, written by the programmed controller, acted upon immediately by the TTU
    6. +
  6. a instruction buffer, written by the programmed controller, acted upon immediately by the TTU
-

The TTU interfaces with the executor, which in turn gates the flow of data through the machine. The executor controls the clock and reset lines, and through this supervises the customer programmed control unit, the CPCU. This two-layer control system is single-threaded and issues the following commands to each selected TTU:

+

The TTU interfaces with the executor, which in turn gates the flow of data through the machine. The executor controls the clock and reset lines, and through this supervises the customer programmed control unit, the CPCU. This two-layer control system is single-threaded and issues the following instructions to each selected TTU:

  1. read(head) → σ
    2. @@ -1334,7 +1334,7 @@
  2. right(head)
-

The head argument multiplexes the command to the specified head. If the TTU has one head, the head argument is optional. The last two commands cause the tape to be moved such that, relatively, the selected head moves left or right by one cell.

+

The head argument multiplexes the instruction to the specified head. If the TTU has one head, the head argument is optional. The last two instructions cause the tape to be moved such that, relatively, the selected head moves left or right by one cell.

The customer programmed control unit, CPCU

@@ -1398,7 +1398,7 @@ +-----------------------------------+ -

The top section has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Immediately to the right of the two toggles are indicator lights. To the right of the indicator lights are two push buttons. One is for reset, which sends the machine back to state q_0, and the other is for stepping the machine when it is in single-step mode. This panel also has an error indicator light which will illuminate if no next state is specified for a state transition, and thus the machine is hung.

+

The top panel has two toggle switches. One turns the machine on, and the other selects run or single-step mode. Immediately to the right of the two toggles are indicator lights. To the right of the indicator lights are two push buttons. One is for reset, which sends the machine back to state q_0, and the other is for stepping the machine when it is in single-step mode. This panel also has an error indicator light which will illuminate if no next state is specified for a state transition, and thus the machine is hung.

The second section is the state transition panel. At the top of this panel are the state indicator lights and a row of halting toggles; if flipped closed, the corresponding state becomes a halting state. Below this is the transition condition matrix, consisting of holes that fit the banana plug ends of a patch cord. Each column corresponds to a current state, and each row corresponds to a status symbol.

@@ -1406,89 +1406,92 @@

Below the transition condition matrix is the destination state row. If the fan-in for a state requires multiple patch cords, a special banana plug adapter can be used, or the patch cords themselves can feature stackable sockets on the back of the plugs, allowing multiple incoming transitions to bridge into a single destination hole.

-

To program the controller, the programmer connects the patch cords. For example, routing a patch cord from the (q_2, s_2) intersection to the q_3 destination hole physically realizes a conditional state transition arc for the controller. If the active status value has no patch cord plugged in at the specific state intersection, the machine evaluates the status default column. If that hole is also empty, the machine utilizes the state default transition hole for the current state. Finally, if no patch cord is plugged in across any of the prior layers, the global default patch cord located at the def intersection is followed.

+

To program the controller, the programmer connects the patch cords. For example, routing a patch cord from the (q_2, s_2) intersection to the q_3 destination hole physically realizes a conditional state transition arc for the controller for the tripple \langle q_2, s_2, q_3 \rangle. If the active status value has no patch cord plugged in at the specific state intersection, the machine evaluates the status default column. If that hole is also empty, the machine utilizes the state default transition hole for the current state. Finally, if no patch cord is plugged in across any of the prior layers, the global default patch cord located at the def intersection is followed.

Below the transition panel are the action selection and symbol selection panels. To enforce the rule that each state executes exactly one action, each state column on the action panel features a single source hole at the top. The programmer routes a patch cord from this source hole down to the desired action row. If the selected action requires a symbol argument, such as write('σ'), a similar routing is performed on the bottom symbol selection panel. Note that this describes the control panel for a single-head, single-TTU machine. Additional patch options would be required to add a TTU device specifier and a head specifier within each TTU.

-

The machine block diagram

- Figure TTCA block diagram -
Figure TTCA block diagram
+ Figure: TTCA block diagram +
Figure: TTCA block diagram
-

This section describes the TTCA machine organization. The diagram above shows the major components and their channels of communications. This instructs designers who will later draft schematics that will specify all of the connections.

+

This section describes the TTCA machine organization. The diagram above shows the major components and their channels of communications. The organization guides designers who will later draft schematics that specify all of the connections.

Components

  1. Control Panel
      -
    1. Executor interface: Power Switch, Single Step Switch, Reset Button, Single Step Button
      2. -
    2. CPCU interface: Patch cord matrices
      3. +
    3. Power Switch, Single Step Switch, Reset Button, Single Step Button
      4. +
    4. patch cord matrices
  2. Executor
      -
    1. Halt state switch bank
      2. -
    2. Clock and phase distribution lines (clk)
      3. -
    3. Reset distribution lines
      4. +
    4. mode control +
        +
      1. power
        2. +
      2. run/step
        3. +
      +
      5. +
    5. staging +
        +
      1. reset button
        2. +
      2. reset logic and distribution lines
        3. +
      3. Halt Switch Bank
        4. +
      +
      6. +
    6. Clock logic and distribution lines (clk)
      7. +
    7. Single Step Switch single shot logic
  3. CPCU (Customer Programmed Control Unit)
    1. One-hot q register
      2. -
    2. Next-state table
      3. +
    3. Next State Table
    4. Action Table
    4. -
  4. g register
    5. -
  5. Status bus
    6. -
  6. Gate Decoder
    7. -
  7. d register
  8. Data bus
    9. +
  9. d register
    10. +
  10. s register
    11. +
  11. Status Decoder
-

As described in the computation theoretic section that is being used as the architectural template, "Computation theoretic TTCA Machine executor", the executor guides the machine through initialization, programmed control, and halting stages of execution. When in the programmed control stage, the CPCU most of the active control comes from the the CPCU. The Executor contains the power, reset, and clock logic. It has two modes of execution, the run mode in which the clock runs free. Secondly, the single step mode, in which clock pulses are sent with the push of a button.

+

As described in the computation theoretic section that is being used as the architectural template, the executor guides the machine through the initialization, programmed control, and halting stages of execution. The Executor contains the power, reset, and clock logic. It has two modes of execution: the run mode in which the clock runs free, and the single-step mode, in which clock pulses are sent with the push of a button. It also holds the halt state switch bank, and is ready to stop the clock when a halt state is reached. When in the programmed control stage, most of the active control comes from the CPCU.

-

The CPCU has the current state register, q, the Next State Table, and the Action Table.

+

The CPCU contains the current state register q, the Next State Table, and the Action Table.

-

The output of the Action Table provides primary control of the running machine. Its output determines which of the TTUs will be active, which head in the TTU is to be used. The machine has an internal data bus. The output of the Action Table also determines which TTU register will drive that bus, and which register will receive data from the bus.

+

The output of the Action Table provides primary control of the running machine. Its output determines which of the TTUs will be active and which head in the TTU is to be used. The machine has an internal data bus. The output of the Action Table also determines which TTU register will drive that bus, and which register will receive data from the bus.

-

The register file contains two registers, g and d. The d register is for holding data read from the tape that will not participate in the next state decision process. The g register holds either data read from the tape, or the status returned from a TTU head. Status is derived from the head's position relative to the ends of the tape. With a real tape drive, an unused leader and trailer are required to prevent the tape from departing from the reels, something that can not be easily undone, so the format, or physical, markers will be on the ends of the usable portion of the tape, rather on the physical end of the tape. The g register gets its name from the fact that its value, independent of the source, is used for gating the next state transition (when the next state comes from the main Next State Table, rather from on from one of the defaults).

+

The register file contains two registers, s and d. Both can receive values from the internal data bus or drive values onto that bus. The d register is not connected to any other units, so it can not participate in the next-state decision process. It can however, be an argument in a subsequent write instruction, causing its value to go back out on the data bus, then to an HU, and then be put back on the tape. The s register is connected directly to the Status Decode, and that in turn is connected directly to the next state logic. The s register can also drive the data bus.

-

The symbols of the alphabet are enumerated such that each symbol corresponds to a specific row index on the control panel. The value on of the g register is decoded, resulting in a one hot encoding of the gate symbol. This one hot encoding then goes to the Next State Table in the CPCU, and illuminates one of the rows. The q register enumerates the columns. If a patch cord is plugged into that intersection point, and leads to the next state bank below, then the next state selected in the next state bank becomes the next state for the machine.

+

The symbols of the alphabet are enumerated such that each symbol corresponds to a specific row index on the control panel. The value of the s register is decoded, resulting in a one-hot encoding of the status symbol. This one-hot encoding then goes to the Next State Table in the CPCU and illuminates one of the rows. The q register enumerates the columns. If a patch cord is plugged into that intersection point and leads to the destination state row below, then the state selected becomes the next state for the machine.

-

The current state register q utilizes a one-hot encoding, allocating a discrete bit per state. A control line from each bit routes to the Halt Switch Bank within the executor, where the outputs are wire-ORed together to generate the master halt signal. Consequently, a halt condition asserts if and only if the currently active state bit corresponds to an enabled toggle in the switch bank. The output of the q register also selects a row in the Action Table.

+

The current state register q utilizes a one-hot encoding, allocating a discrete bit per state. A control line from each bit routes to the Halt Switch Bank within the executor, where the outputs are wire-ORed together to generate the master halt signal. Consequently, a halt condition asserts if and only if the currently active state bit corresponds to an enabled toggle in the switch bank. The output of the q register also selects a row in the Action Table, and this is key to controlling the machine.

- -

Upon reset, the current state register initializes to a one-hot configuration with the bit for state q_0 asserted, while all other machine registers clear to zero. To prevent power-on initialization hazards—where unlatched logic could trap the machine in an illegal configuration, ignore subsequent reset commands, or induce physical hardware damage—the power switch incorporates a capacitor timer that maintains an active reset signal until supply voltages fully stabilize.

- -

- This design assumes that releasing the reset line causes the machine to begin execution immediately. While adequate for our baseline model, a deluxe variant would integrate a dedicated 'go' button and associated transition logic. -

+

Upon reset, the current state register initializes to a one-hot configuration with the bit for state q_0 asserted, while all other machine registers clear to zero. Uncontrolled power-up could trap the machine in an illegal configuration where it would ignore subsequent reset instructions or even induce physical hardware damage. To prevent initialization hazards, the power switch incorporates a capacitor timer that maintains an active reset signal until supply voltages fully stabilize. When in run mode, the machine will begin running after reset is released. In single step mode, it will then wait for a push of the single step button.

The tape transport unit, TTU, handles mounting, unmounting, reading, writing, and moving the tape. In this volume, we treat head motion in a relative sense, recognizing that a physical TTU moves the magnetic tape beneath a stationary head rather than displacing the head across the tape. Our architecture allows a system to incorporate multiple TTU modules, each containing its own read buffer, status buffer, and head assembly. Tapes can be dynamically mounted, unmounted, shelved, and transferred between any TTU on the same machine or across distinct systems.

-

- The hardwired executor must not be conflated with the Customer Programmed Control Unit. For a microcode-controlled machine, the executor's phase sequencing procedure resides in microcode memory and executes much like a stored program, independent of the customer's payload logic. Alternatively, in a hardwired implementation, the executor logic is expressed directly via discrete logic gates and flip-flops. Whether a machine relies on microcode or hardwired logic for its internal sequencing is strictly a question of implementation, leaving the underlying architectural constraints and the CPCU interface invariant. -

+

Description of a read('s') instruction

-

Description of a read_g command

+

The current state register, q, samples and holds on the rising edge of the clock. This then provides a stable state signal to the control panel for an entire cycle. The status register, s, is the phase inverse; it samples on the falling edge of the clock and holds for an entire cycle.

-

The current state latch, q, is open on the falling edge of the clock, and then samples and holds while the clock is high. The gate register, g, is the phase inverse; it is open while the clock is high, and samples and holds while the clock is low.

+

On the rising edge of the clock, the new current state signal ripples through the Action Table. As the q register is stored as a one-hot value, this happens very quickly. Rather than placing instructions in the Action Table, the decoded values of the instructions with the control signals that are needed are programmed directly into the table. Among the decoded outputs of the action instruction is a control signal that enables the status register to sample when the clock falls.

-

On the rising edge of the clock, the state is latched. The current state signal ripples through the Action Table. As the q register is stored as a one-hot value, this happens very quickly. Rather than placing commands in the Action Table, the decoded values of the commands that are needed for control are programmed directly into the table. Among the decoded outputs of the action command is a control signal that enables the opening of the gate register latch.

+

A control signal from the decoded instruction coming from the Action Table then enables the selected TTU and provides it with its decoded instruction. Part of the decode will be the HU select line, and a signal to tell the HU status register to drive the machine's internal data bus.

-

A control signal from the decoded command coming from the Action Table then enables the selected TTU. If the TTU command is already decoded, a line will select either the TTU read register (for the read_d command) or the selected status register (for the read_g command). Both values are ready to drive the bus when the control signal arrives.

+

Thus the status register in the selected TTU and HU will be driving the data bus, and the machine s register is ready to sample the bus. Then the clock falls, the s register updates, and holds its value until the next time when it is enabled to update and the clock falls.

-

At this time the g latch is enabled and open, so the selected value travels through the latch to a decoder, and then to the state transition table, where it energizes a row, reaches the patch cord, and the signal travels through the patch cord and illuminates the next state bit. This is completes the critical path that sets the clock period.

+

The updated value in the s register then drives the Next State Table rows. The column lines stabilized earlier in the cycle, immediately after the state updated. If a patch cord is plugged in at the intersection of the row and the column, then a signal will travel through that cord to the next state input sub-panel that is located below the state and status matrix. Then when the clock rises again, this signal, which is held steady by the driving status register, will be sampled and become the next state.

-

During that time the clock has a falling edge, so the g register latches and holds the gate value. The q register latch opens, waiting for the critical path signal to resolve. It has the remaining low period of the clock to do so, giving it one full clock cycle to resolve.

+

Then the clock rises, and the cycle repeats, though perhaps while selecting a different row from the action table, and thus performing a different instruction.

-

Then the clock rises, and the cycle repeats.

+

It has been common in real machine design that instead of using one clock and controlling its duty cycle, that two phase separated clocks are used. Then all registers can sample on the rising (or falling edge), and the separation between the phases can be adjusted to optimize the timing. With this approach any number of phrase separated clocks could be introduced. It is also possible that a single clock could be used, where the new state drives the loop and the s register stands to the side, also sampling on rising edge only so that it can later drive the bus in a later write command.

The TTCA stored program @@ -1864,7 +1867,7 @@

- Consider an illustrative example. We start by defining a fundamental language for communicating with the head and tape transport unit. The statements we communicate to our tape transport unit will be explicit physical commands: (step), (left), (read), and (write symbol). In the first order, evaluating these commands physically actuates the tape. + Consider an illustrative example. We start by defining a fundamental language for communicating with the head and tape transport unit. The statements we communicate to our tape transport unit will be explicit physical instructions: (step), (left), (read), and (write symbol). In the first order, evaluating these instructions physically actuates the tape.

@@ -1898,7 +1901,7 @@

- For the second order difference operation, we compose the ASTs to create a new program. Here we extract the body of the second operand's AST and substitute every (write s) followed by a (step) command with an inverted pair: a (left) command followed by writing the empty symbol (write □). + For the second order difference operation, we compose the ASTs to create a new program. Here we extract the body of the second operand's AST and substitute every (write s) followed by a (step) instruction with an inverted pair: a (left) instruction followed by writing the empty symbol (write □).

@@ -2017,7 +2020,7 @@ ;; (write s) (step)) -

This technique of composing Turing Machine programs in the presence of simplification is closely related to that of symbol computation and expression simplification that we find in math tools such as Mathematica. We can imagine our Turing Machines as functions with names, and then symbolic computation leaves them unevaluated as here. Then the Mathematica Simplify is the compiler optimization simplifier as above. A difference in these two systems is that of the functions being reduced to Turing Machine head and tape transport unit commands.

+

This technique of composing Turing Machine programs in the presence of simplification is closely related to that of symbol computation and expression simplification that we find in math tools such as Mathematica. We can imagine our Turing Machines as functions with names, and then symbolic computation leaves them unevaluated as here. Then the Mathematica Simplify is the compiler optimization simplifier as above. A difference in these two systems is that of the functions being reduced to Turing Machine head and tape transport unit instructions.

The multiplicative inverse of the additive identity

@@ -3022,7 +3025,7 @@

Various portions of this text have mentioned calling a Turing Machine as a subroutine. This is described as unmounting the tape from the calling machine, mounting it on the subroutine machine, running the subroutine machine until it halts, then unmounting the tape from the subroutine machine, and mounting it back on the calling machine. However, this would be a manual process. To automate the process, we use a Universal Turing Machine. It has the definition for the calling machine and the subroutine machine on its tape. We can add an additional tape to the machine to hold the stack. Then a subroutine call happens much as it does in conventional software.

-

A gasket machine is actually a set of subroutines with one corresponding to each of the tape transport commands. +

A gasket machine is actually a set of subroutines with one corresponding to each of the tape transport instructions.

@@ -3169,7 +3172,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

If a Turing Machine does nothing then halts, it will implement an identity relationship between input and output. If we do not want the input given to a machine to 'bleed through', we will have to erase it. A computational TTCA Machine starting from a null tape can only produce finite tapes, so T1 can erase whatever T0 writes to the tape. However, if we are analyzing, instead of running the TTCA Machine, we might discover that the tape length would be infinite if the machine could be run. We know that if we pass an infinite tape to a computational TTCA Machine, it would not be able to erase the tape. Fortunately we can derive this fact through analysis and proof without having to run the computational machine to see if it erased the tape.

-

Hence if we allow for infinite inputs, we should add an 'erase-to-end-of-tape' command to our machines, so that the computational machines may leave a tape with only their outputs on them. Our erase-to-end-of-tape command will be executed in a single step.

+

Hence if we allow for infinite inputs, we should add an 'erase-to-end-of-tape' instruction to our machines, so that the computational machines may leave a tape with only their outputs on them. Our erase-to-end-of-tape instruction will be executed in a single step.

Once an input tape is mounted, T0 is a computational TTCA Machine given a finite tape, its output is a finite tape, and that is taken to be the input for T1.

@@ -3310,9 +3313,9 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

Address of an area

-

The address of a cell is the number of steps required to reach the cell when starting from the leftmost cell on the tape. The leftmost cell has an address of zero. It might seem intuitive to set the address of an area on the tape to be that of the first cell in the area. If we require that an area have at least one cell to exist, this approach works even for machines with a cell delete command.

+

The address of a cell is the number of steps required to reach the cell when starting from the leftmost cell on the tape. The leftmost cell has an address of zero. It might seem intuitive to set the address of an area on the tape to be that of the first cell in the area. If we require that an area have at least one cell to exist, this approach works even for machines with a cell delete instruction.

-

Suppose that we are deleting the cells in an area. The delete command affects the cell to the right of the cell the head is on. Hence to delete all the cells of an area, the head is placed on the left neighbor cell to the area. Say that we delete an area of three cells. We will call delete three times. It seems unsatisfactory to say the area no longer exists after the three deletes because the head locating the area never moved. I.e. we still have a location marker for the area, so we could, for example, call append and put a cell back into the area. For the area to truly not exist, it would not have a location.

+

Suppose that we are deleting the cells in an area. The delete instruction affects the cell to the right of the cell the head is on. Hence to delete all the cells of an area, the head is placed on the left neighbor cell to the area. Say that we delete an area of three cells. We will call delete three times. It seems unsatisfactory to say the area no longer exists after the three deletes because the head locating the area never moved. I.e. we still have a location marker for the area, so we could, for example, call append and put a cell back into the area. For the area to truly not exist, it would not have a location.

Thus it seems more satisfactory to locate an area by its left neighbor cell, than to locate it by its leftmost cell.

@@ -3374,7 +3377,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

For a given Turing Machine, the input is the sole determiner of the output. I.e. each time the same input is given, we get the same output. The input and output are mathematical objects, hence Turing Machines are functions. However, it is common in computer science to speak of Turing Machines as 'solving problems' rather than saying they are functions. This is because we often think of the inputs and outputs of Turing Machines as being something other than mathematical objects. For example, when a Turing Machine sorts sequences found on its input, we might say that it solves a sorting problem.

-

Turing Machines will differ due to differing alphabets, state controller graphs, associated commands, start, and halt states. The choice of empty-symbol is inconsequential as long as it is distinct from the alphabet. As we will see in the later discussion on variations, the choice of alphabet is not very important. For two alphabets of the same cardinality we can setup a one to one mapping, and for those of differing cardinalities we can use sequences of alphabet symbols that map to alphabet symbols. For example, given an alphabet of ‘T’ and ‘F’, and a second alphabet of ’t’, ‘f’, ‘x’, ‘z’ we may make the following map:

+

Turing Machines will differ due to differing alphabets, state controller graphs, associated instructions, start, and halt states. The choice of empty-symbol is inconsequential as long as it is distinct from the alphabet. As we will see in the later discussion on variations, the choice of alphabet is not very important. For two alphabets of the same cardinality we can setup a one to one mapping, and for those of differing cardinalities we can use sequences of alphabet symbols that map to alphabet symbols. For example, given an alphabet of ‘T’ and ‘F’, and a second alphabet of ’t’, ‘f’, ‘x’, ‘z’ we may make the following map:

f @@ -3392,7 +3395,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

Then given this mapping, we may use two cells for each one cell for any {‘f’, ‘t’, ‘x’, ‘z’} alphabet machine, and then use the only the {‘T’, ‘F’} alphabet.

-

There are a countably infinite number of permutations for alphabets, state controller graphs, associated commands, start and halt states, hence there are a countably infinite number of Turing Machines that fit our definition. However, there are an uncountably infinite number of mathematical functions. Consequently, we must expect that some functions cannot be computed with Turing Machines.

+

There are a countably infinite number of permutations for alphabets, state controller graphs, associated instructions, start and halt states, hence there are a countably infinite number of Turing Machines that fit our definition. However, there are an uncountably infinite number of mathematical functions. Consequently, we must expect that some functions cannot be computed with Turing Machines.

There might be multiple Turing Machines that perform the same function. A set of such machines forms a functional equivalence class. Within a functional class there will be a class of members related in that they all use the smallest number of steps when considered against the limit of input length. We discuss this further in the section on complexity.

@@ -3496,7 +3499,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

In a variation on the run it twice approach, instead of running the first machine, we might instead analyze it and should we be able to surmise a maximum tape length, we could use that.

-

In yet another approach we can extend the finite tape as needed. We place a control layer over the finite tape. When a step right command from the Turing controller invokes the right from rightmost error, the lower layer allocates memory, lengthens the tape, and then performs the requested step right. As long as this occurs in fixed time, (or of sufficient lesser order time than the dominate order of the time complexity), and as long as there is indeed more memory to allocate - this Turing Machine variation will yield the same order of computational complexity as one with an an infinite tape.

+

In yet another approach we can extend the finite tape as needed. We place a control layer over the finite tape. When a step right instruction from the Turing controller invokes the right from rightmost error, the lower layer allocates memory, lengthens the tape, and then performs the requested step right. As long as this occurs in fixed time, (or of sufficient lesser order time than the dominate order of the time complexity), and as long as there is indeed more memory to allocate - this Turing Machine variation will yield the same order of computational complexity as one with an an infinite tape.

I propose the following Turing Machine variation:

@@ -3515,13 +3518,13 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos fixed procedure for using these -

In our original Turing Machine model, the controlling state machine commands were limited to, do-nothing, left, right, write, with reading as an implied command. To this list we add append. The append command may only be called when the head is on the rightmost tape cell. This is not limiting because the command may be called from a state that is at the end of an arc triggered by the right from rightmost error. When we have no empty-symbol, append is given an alphabet symbol and performs a write into the new cell. This is not limiting because if need be, a person can always perform an extraneous write of an alphabet symbol.

+

In our original Turing Machine model, the controlling state machine instructions were limited to, do-nothing, left, right, write, with reading as an implied instruction. To this list we add append. The append instruction may only be called when the head is on the rightmost tape cell. This is not limiting because the instruction may be called from a state that is at the end of an arc triggered by the right from rightmost error. When we have no empty-symbol, append is given an alphabet symbol and performs a write into the new cell. This is not limiting because if need be, a person can always perform an extraneous write of an alphabet symbol.

With this extendable tape model all Turing Machine components remain finite during computation, though some are arbitrarily large. This variation is more suited for creating a mapping between a Turing Machine and a real program running on a real machine. Specifically, a computation requiring N cells maps exactly to a physical machine possessing at least N cells. The theoretical model and the physical implementation remain perfectly isomorphic provided the physical environment does not exhaust its memory bounds. Because a computational TTCA machine demands strictly finite tape extensions, a physical machine that completes the execution maintains exact structural correspondence. This isomorphism holds continuously as long as memory remains available, even accommodating dynamic hardware expansion such as memory hot-swapping. The theoretical correspondence fails solely upon a hard physical limit being reached during execution.

-

More about commands

+

More about instructions

-

The Turing Machine state controller has a command symbol tied to each state. The Turing Machine procedure then has us take action based on this symbol. This is our current command set:

+

The Turing Machine state controller has a instruction symbol tied to each state. The Turing Machine procedure then has us take action based on this symbol. This is our current instruction set:

right, causes the head to move to the right neighbor cell. @@ -3535,16 +3538,16 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

We will also include the inverse function for append. delete(append(x)) reads x while deleting the cell that x was in. The current Turing Machine model can emulate this function by shifting all the symbols in cells the right of the head left by one, and then simply not using the rightmost cell.

-

We are also going to support multiplexed state controllers. Our multiplexed Turing Machine will have multiple heads. One for each separate thread of execution through the state controller. As explained in the following chapters, supporting multiplexing makes our machine more complex, especially in the presence of the delete command. However, we defer that discussion to the relevant chapters.

+

We are also going to support multiplexed state controllers. Our multiplexed Turing Machine will have multiple heads. One for each separate thread of execution through the state controller. As explained in the following chapters, supporting multiplexing makes our machine more complex, especially in the presence of the delete instruction. However, we defer that discussion to the relevant chapters.

-

In cases where successive states are visited in a fixed order it is convenient to combine the commands. We have developed the concept of a command statement to support this:

+

In cases where successive states are visited in a fixed order it is convenient to combine the instructions. We have developed the concept of a instruction statement to support this:

- statement::[direction]command+[modifier][&contract]*[arg]* + statement::[direction]instruction+[modifier][&contract]*[arg]* direction::- | ε - command::r | w | s | a | d | m | e | ☥ + instruction::r | w | s | a | d | m | e | ☥ modifier::◧ ◨ n - command + instruction r read cell under the head w write cell under the head s step @@ -3565,22 +3568,22 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos a◧ ; make a new leftmost cell a◨ ; append to rightmost sn ; step n times - to derive a longer command, combine them: + to derive a longer instruction, combine them: as ; append then step -a-s ; append to the left, step to the left -

The left direction is specified with a minus sign, otherwise the direction is taken as right going. So the letter s is the right command, and -s is the left command. The command s3 steps right three times.

+

The left direction is specified with a minus sign, otherwise the direction is taken as right going. So the letter s is the right instruction, and -s is the left instruction. The instruction s3 steps right three times.

-

The command a appends and writes a new cell to the right of the head. We use two special characters from the UTF character set to signify the rightmost and leftmost of the tape. This one looks like a little tape with its left cell inked in, ◧, so we use it to stand for leftmost. We use this one, ◨, to mean rightmost. Hence a◨ makes a new rightmost cell, and a◧ makes a new leftmost cell.

+

The instruction a appends and writes a new cell to the right of the head. We use two special characters from the UTF character set to signify the rightmost and leftmost of the tape. This one looks like a little tape with its left cell inked in, ◧, so we use it to stand for leftmost. We use this one, ◨, to mean rightmost. Hence a◨ makes a new rightmost cell, and a◧ makes a new leftmost cell.

-

In some cases it is possible to implement higher performance implementations for commands when the programmer tells us some additional information. For example a◨&h◨ has identical functionality as a◨, while the programmer also guarantees that we are on the rightmost cell. This saves the function from having to scan to the end of the tape.

+

In some cases it is possible to implement higher performance implementations for instructions when the programmer tells us some additional information. For example a◨&h◨ has identical functionality as a◨, while the programmer also guarantees that we are on the rightmost cell. This saves the function from having to scan to the end of the tape.

-

We can concatenate the command letters into a string to summarize what would happen sequentially in adjacent state transitions. If these compound commands need arguments, then they are pulled from the argument list in order as they are needed. For example, as means to append, with the parameter for the append taken from the argument list, and then to step.

+

We can concatenate the instruction letters into a string to summarize what would happen sequentially in adjacent state transitions. If these compound instructions need arguments, then they are pulled from the argument list in order as they are needed. For example, as means to append, with the parameter for the append taken from the argument list, and then to step.

-

We support multiplexing with the command e, which is short for entangled. This operator returns what appears to be a second independent machine, but this apparently independent second machine actually shares the same tape with the first machine. It is functionally identical to giving one machine two heads, and thus the ability to have state sets.

+

We support multiplexing with the instruction e, which is short for entangled. This operator returns what appears to be a second independent machine, but this apparently independent second machine actually shares the same tape with the first machine. It is functionally identical to giving one machine two heads, and thus the ability to have state sets.

-

The command esr is a compound command referring to sequentially applying three other commands. The e says to make an entangled copy of the head. The s says to step this copy, and the r says to do the read. The analogous esw does a write as the last step. This sort of combination of letters to make more complex commands was inspired by Lisp's car and cdr compositions. Though this is functionally what the command does, its actual implementation might be completely different.

+

The instruction esr is a compound instruction referring to sequentially applying three other instructions. The e says to make an entangled copy of the head. The s says to step this copy, and the r says to do the read. The analogous esw does a write as the last step. This sort of combination of letters to make more complex instructions was inspired by Lisp's car and cdr compositions. Though this is functionally what the instruction does, its actual implementation might be completely different.

The combination of multiplexing and cell deletion leads to a hazard where one thread can delete a cell the head is on in another thread. We add a collision error continuation to our multiplexed Turing Machine interface because of this situation.

@@ -3717,7 +3720,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

The Turing Machine, and our variation of it, may be partitioned into two parts. One part of the part consists of the tape head and the tape. We call this the Tape Transport Unit, as that is the name used for the mechanism that does this work on real tape storage units. The other part of the part is the Controller.

-

The Tape Transport Unit is given commands for reading, writing, and moving the head. (In real Tape Transport Units the head is in a fixed position and we move the tape, but the relative affect is the same.) Our modified model adds commands for extending the tape. During normal operation these commands only come from the controller.

+

The Tape Transport Unit is given instructions for reading, writing, and moving the head. (In real Tape Transport Units the head is in a fixed position and we move the tape, but the relative affect is the same.) Our modified model adds instructions for extending the tape. During normal operation these instructions only come from the controller.

We have two types of controllers. One type of controller is a state machine. Its design is an integral part of the Turing Machine. To step the Turing Machine means to step this state machine to its next state. The state machine definition exists before the Turing Machine takes its first step, and its definition remains intact for as long as said Turing Machine exists.

@@ -3731,7 +3734,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

Installing the library

-

TM is presented as an iteration library on the de facto package manager for Lisp quicklisp. Alternatively, a person may clone the repository www.github.com/Thomas-Walker-Lynch/tm and then checkout the latest release tag, which as of this writing is v0.7-alpha. After installing the code cd into the tm directory and run your lisp interpreter. Inside your lisp interpreter type the commands (load “load”) and (test-all). test-all should return with a message that all of the tests passed.

+

TM is presented as an iteration library on the de facto package manager for Lisp quicklisp. Alternatively, a person may clone the repository www.github.com/Thomas-Walker-Lynch/tm and then checkout the latest release tag, which as of this writing is v0.7-alpha. After installing the code cd into the tm directory and run your lisp interpreter. Inside your lisp interpreter type the instructions (load “load”) and (test-all). test-all should return with a message that all of the tests passed.

It is possible that the threading tests, 'ts1-' might fail if your machine is heavily loaded or very slow, as they have timing built into them, but this is unlikely. Then type either (use-package :tm) or (in-package :tm) depending on what your objectives are.

@@ -3773,13 +3776,13 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos * -

Notice I used git tag to see the releases. At this time, v0.7-alpha is the latest, so I checked that out. If you want the unstable latest code rather than the stable latest release, leave out the git checkout command.

+

Notice I used git tag to see the releases. At this time, v0.7-alpha is the latest, so I checked that out. If you want the unstable latest code rather than the stable latest release, leave out the git checkout instruction.

-

The TM Library makes use of Unicode. There is no getting around it. This is discussed further in the next section. In addition TM defines synonyms for commands such as 'not equal', which is the one command shown at the end of the transcript given above.

+

The TM Library makes use of Unicode. There is no getting around it. This is discussed further in the next section. In addition TM defines synonyms for instructions such as 'not equal', which is the one instruction shown at the end of the transcript given above.

Unicode usage

-

For your convenience there is a file "emacs-keys" in the docs directory of the distribution. It sets the C-x g name SPC command to enter one of the Unicode characters that are used in the library. Here 'name' is a nickname.

+

For your convenience there is a file "emacs-keys" in the docs directory of the distribution. It sets the C-x g name SPC instruction to enter one of the Unicode characters that are used in the library. Here 'name' is a nickname.

So to type the character capital delta after emacs-keys has been loaded, type C-x g D SPC. Actually Δ occurs twice in Unicode, once as capital delta, and once as a symbol for 'increment' in mathematics. We consider the increment version to only be there for typography purposes. We only use capital delta, even when it is for an increment variable.

@@ -3791,7 +3794,7 @@ Now suppose defining a Turing Machine that initially has the head on the leftmos

We use '➜' in continuation function names, and '⟳' as a loop operator.

-

The ◧ and ◨ symbols are used in compound command names and for access language statements to indicate operation on rightmost or leftmost rather than the cell the head is on, or, to specify contracts with the programmer of the sort: "this function is only called when the cell is on rightmost."

+

The ◧ and ◨ symbols are used in compound instruction names and for access language statements to indicate operation on rightmost or leftmost rather than the cell the head is on, or, to specify contracts with the programmer of the sort: "this function is only called when the cell is on rightmost."

Since I had symbols for leftmost and rightmost, I started using them generally to mean leftmost or rightmost wherever it was convenient. For example, to shorten up the names of continuations so that parameter lists would fit on a line.

diff --git a/document/book/TTCA_machine.svg b/document/book/TTCA_machine.svg index 1016e6b..5843f1e 100644 --- a/document/book/TTCA_machine.svg +++ b/document/book/TTCA_machine.svg @@ -22,15 +22,15 @@ inkscape:pagecheckerboard="0" inkscape:deskcolor="#d1d1d1" showgrid="true" - inkscape:zoom="0.905042" - inkscape:cx="550.25071" - inkscape:cy="447.49304" + inkscape:zoom="1.7791439" + inkscape:cx="177.05144" + inkscape:cy="370.96492" inkscape:window-width="1920" inkscape:window-height="1131" inkscape:window-x="0" inkscape:window-y="32" inkscape:window-maximized="1" - inkscape:current-layer="svg311">Gate DecoderStatus Decoder== σ== s0 == leftmost== s1==rightmost== s2...